Please use this identifier to cite or link to this item: http://dspace.dtu.ac.in:8080/jspui/handle/repository/14305
Full metadata record
DC FieldValueLanguage
dc.contributor.authorRathi, Rounak J-
dc.date.accessioned2015-05-14T11:47:36Z-
dc.date.available2015-05-14T11:47:36Z-
dc.identifier.urihttp://dspace.dtu.ac.in:8080/jspui/handle/repository/14305-
dc.description.abstractEnergy dissipation being an important concern in VLSI design, made designers to look for alternative logic styles such as reversible logic gate having lower power consumption. Reversible circuits are those circuits that do not lose information as the amount of energy dissipated in a system has a direct relationship to the number of bits erased during computation and the number of bits lost in reversible circuits is zero, so it doesn’t lose energy. These circuits can generate unique output vector from each input vector, and vice versa therefore, there is a one-to-one mapping between the input and output vectors. The important cost metrics in the design and synthesis of reversible logic circuits are the quantum cost, delay and the number of garbage outputs Now a days, due to the necessity for low-power design and the emerging field of nanotechnology, reversible computing has become more attractive. It plays an important role in the field of low-power circuit designs and computational nanotechnology. They can also be used to design low power arithmetic and data path units for digital signal processing applications, such as the designs of low power adders, multipliers, FFT, IDCT etc, and quantum computers In this work available 2x2, 3x3 and 4x4 reversible logic gates are reviewed and a new 5x5 reversible logic gate called ABCD gate is proposed, which provides more logic function implementation than available 5x5 logic gates. More specifically basic gates and universal gates, Half adder, Half subtractor, Decoder/Demux, One bit Comparator, Even Parity detector ,Odd parity detector, Even Parity generator, Odd parity generator and Equality Detector can be implemented. The proposed ABCD gate is compared with the existing 5x5 gates in terms of parity preserving logic, constant input, garbage output, total logical calculations.en_US
dc.description.sponsorshipDr. Neeta Pandey Associate Professor, ECE Departmenten_US
dc.language.isoenen_US
dc.relation.ispartofseriesTD-1263;-
dc.subjectQuantum Computersen_US
dc.titleDESIGN OF REVERSIBLE LOGIC GATES AND THEIR APPLICATIONSen_US
dc.typeThesisen_US
Appears in Collections:M.E./M.Tech. Electronics & Communication Engineering

Files in This Item:
File Description SizeFormat 
MTECH THESIS.pdf2.35 MBAdobe PDFView/Open
thesisy.pdf645.15 kBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.