Dynamic Power Optimization of 1-Bit CMOS Full Adder Using Genetic Algorithm

Abstract

With every passing day, integrated circuits are gaining importance, the size of components is reducing and the number of elements that can be fabricated on a single chip has increased many folds in the past decade. With the ongoing globalization and technology the power requirements of mankind are rising at an extremely high rate. Here we are making an attempt to optimize the power consumed by VLSI circuits. The circuit under consideration is a simple full adder implemented using CMOS technology. The circuit utilizes 28 transistors and runs on a high frequency in the range of MHz. The circuit has three inputs (A,B & C) and two outputs(Sum and Carry) We have implemented Genetic algorithm to solve the given problem. The thesis is mainly divided in to two portions. In the first half we try to find out the maximum and minimum acceptable values and other constraints on which power depends. We utilized the Cadence, Virtuso- 4 software to manually find these values. In the second half the values obtained in previous step are utilized to create the initial population. We define the fitness function and other necessary parameters. MATLAB applies the genetic algorithm and finds us an optimum solution. Since Genetic algorithm is heuristic in nature it might not give us the ideal result but surely the outputs are reasonably good.