Please use this identifier to cite or link to this item: http://dspace.dtu.ac.in:8080/jspui/handle/repository/14197
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dc.contributor.authorDUHAN, PRADEEP-
dc.date.accessioned2012-09-19T06:02:11Z-
dc.date.available2012-09-19T06:02:11Z-
dc.date.issued2012-09-19-
dc.identifier.urihttp://dspace.dtu.ac.in:8080/jspui/handle/repository/14197-
dc.description.abstractIn the past few decades the minimum size of transistor has been downscaled according to the Moore's law. But now further downscaling of MOSFET is facing challenges like SCE(short channel effects), gate insulator tunnelling. To overcome these challenges FinFET, a type of multigate device, is the most promising device structure. FinFET technology has the calibre to continue with the Moore’s law. FinFET has started replacing conventional MOSFETs. The gate in FinFET is wrapped around a thin silicon fin for better control over the conducting channel i.e. fins. 3nm FinFET has been demonstrated in university labs. This thesis analyses the effects of variation in fin width, fin height, oxide thickness on the various device parameters like drain current(Ion), leakage current(Ioff), threshold voltage(Vt), DIBL and subthreshold swing(S) of FinFET by using simulation tools 3D Silvaco ATLAS version5.16.3.R and Devedit version 2.6.0.R. Analysis has also been done by using high-k dielectric materials like Hafnium oxide(HfO2), Silicon Nitride(Si3N4), and Aluminium oxide(Al2O3)for gate material instead of conventional gate material Silicon dioxide.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesTD 1119;56-
dc.subjectFinFETen_US
dc.subjectTRANSISTORen_US
dc.subjectMOSFETsen_US
dc.subjectDIBLen_US
dc.titleSIMULATION OF DOUBLE GATE SOI FINFETen_US
dc.typeOtheren_US
Appears in Collections:M.E./M.Tech. Applied Physics

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