FREQUENCY SYNTHESIZING USING PHASE LOCK LOOP FOR HIGH FREQUENCY APPLICATIONS

Abstract

Increase in demand for affordable high performance communication devices, particularly in mobile systems, is the driving force behind the development of high speed, low cost and low-power circuits in CMOS technology. This is mainly due to the fact that CMOS process facilitates the integration of analog and digital circuits on the same chip. A major technique to reduce the power consumption in a CMOS chip is the use of low swing signalling. Integrated phase locked loops(PLL’s) are the versatile components in many communication and control applications. PLL’s are the integral part of many communication and computing applications.. The designed PLL operates from a single 1.5 Volts supply and its frequency range of operation is upto 1.8 giga hertz. The phase locked loop each individual components such as Phase frequency detector, charge pump, loop filter, Voltage control oscillator and divider is designed for frequency synthesizing. The PLL is designed and simulated in a 130 nano metres standard CMOS technology