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dc.contributor.authorOJHA, RAM MOHAN-
dc.date.accessioned2012-09-17T05:38:21Z-
dc.date.available2012-09-17T05:38:21Z-
dc.date.issued2012-09-17-
dc.identifier.urihttp://dspace.dtu.ac.in:8080/jspui/handle/repository/14145-
dc.description.abstractThe analog electronics circuits have been developed much better from the past few decades. The design of analog amplifier has become the field of attraction due to various changes in technology. Amplifier circuits are analog circuit which can be used anywhere in houses like in electronic appliances. A variety of these devices such as Operational Amplifier, Fully Differential Amplifier, Current Feedback and Current Conveyors are spread all over in the integration of such electronic devices. In analog processing system Operational Amplifier is considered as a key element. A CMOS single output two stage operational amplifier is presented which operates at 1.8 V power supply. It is designed to meet a set of provided specifications. The unique behavior of MOS transistor in sub-threshold region allows designer to work at both low input bias current and also at low voltage. This op-amp has very low standby power consumption with a high driving capability and operates at low voltage so that the circuit operates at low power. The op-amp provides a gain of 95.2 dB, -3db bandwidth of 80 Hz, phase margin of 64.60 and a unity gain bandwidth of 1.49 MHz for a load of 1 pF capacitor. This op-amp has a PSRR of 148.2 dB. It has a CMRR (dc) of 99.1 dB, and an output slew rate of 11.9 V/μs. The power consumption for the op-amp is 54.2 μW. The presented op-amp has Input Common Mode Range (ICMR) of 0.2V to 1.3V. The op-amp is designed in the 180 nm technology using the 180 nm technology library. The described op-amp is a simple two stage single ended op-amp which employs composite cascode technique. The input stage of the op-amp is a differential amplifier with an NMOS pair. The second stage of the operational amplifier is a simple PMOS common source amplifier. The second stage is used to increase the voltage swing at the output. The schematic of the operational amplifier has been designed and simulation is done using PSPICE simulator thereafter results are compared with the previous reported design.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesTD 1008;102-
dc.subjectHIGH GAIN LOW POWERen_US
dc.subjectAMPLIFIERen_US
dc.subjectPSPICEen_US
dc.subjectPMOSen_US
dc.subjectCMOSen_US
dc.subjectANALOG ELECTRONICSen_US
dc.titleDESIGN OF HIGH GAIN LOW POWER AMPLIFIERen_US
dc.typeThesisen_US
Appears in Collections:M.E./M.Tech. Electronics & Communication Engineering

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cover page Ram Mohan Ojha.pdfCOVER43.75 kBAdobe PDFView/Open
front pages Ram Mohan Ojha.pdfCERTIFICATES255.85 kBAdobe PDFView/Open
thesis last page Ram Mohan Ojha.pdfCHAPTER4.91 MBAdobe PDFView/Open


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