A NEAR ACCURATE, ULTRA FAST, EARLY PEAK CURRENT ESTIMATOR REQUIRING MINIMUM DESIGN IMPUTS

Abstract

In today’s complex IC design one of the major points is to estimate a priori the peak current demand of the core logic. It is always desired to know what will be the current consumption of the device during the architecture definition phase of the device. The knowledge of peak current enables the designer to fix the architecture resources like: 1) On chip decoupling capacitance requirement. 2) Regulator specification. 3) Types of clock tree buffer to be kept. 4) EMC estimation, etc… All these resources need to be defined during the costing and architecture exploration phase of design. Any wrong estimation on these critical points can lead to big surprises caught only in very late stage of the design cycle where there are established flow to estimate the peak current. This leads to either re-spinning the entire design cycle to its starting phase or leading to closure of the project in-between. In this thesis work, we had developed a simple yet very powerful analytical expression for analyzing the peak current. This analytical expression is a general expression and can be applied to the peak current evaluation coming out from either our flow or any other tool. Finally, a CAD tool called KAPLANA was developed to efficiently determine the peak current of the complex core logic at architectural definition phase. Determination of peak current during the design phase would be extremely beneficial to circuit designers. This would reduce the turn around time for circuits and prevent costly redesign. KALPANA provides a high degree of accuracy as compared to other tools available which can estimate the current at very late phase of the design cycle.