DESIGN AND ANALYSIS OF LOW POWER AND STABLE 7T CELL BASED SRAM

Abstract

The design of a seven transistors (7T) SRAM cell is carried out in this project for enhancing the data stability and the read speed while simultaneously reducing the active and standby mode power consumption . With the 7T SRAM cell, the storage nodes are isolated from the bitlines during a read operation, thereby enhancing the data stability as compared to the standard six transistors (6T) SRAM circuits. The transistors of the cross-coupled inverters are not on the critical read delay path with the new technique. The design criteria of access and core mosfets for the read and write operation is analyzed in detail for significantly increasing write and read stability and active power consumption without causing a degradation in the read speed. A performance comparison vis-a-vis the 6T cell for different parameters is carried out. With the designed 7T SRAM circuit, the read noise margin and the read speed are enhanced by up to 90% and 25%, respectively, as compared to the conventional 6T SRAM circuits. Furthermore, the leakage power consumption of 7T SRAM circuit is reduced by up to 38%, as compared to the conventional 6T SRAM circuits in a 180nm CMOS technology.