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DC Field | Value | Language |
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dc.contributor.author | KUMAR, AJAY | - |
dc.date.accessioned | 2011-12-15T07:09:28Z | - |
dc.date.available | 2011-12-15T07:09:28Z | - |
dc.date.issued | 2011-12-15 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/13879 | - |
dc.description | M.TECH | en_US |
dc.description.abstract | This thesis presents the theory and a design method for distributed digital phase shifters, where both the phase‐error bandwidth and the return‐loss bandwidth are considered simultaneously. The proposed topology of each phase bit consists of a transmission‐line (TL) branch and a bandpass filter (BPF) branch. The BPF branch uses grounded shunt quarter wavelength stubs to achieve phase alignment with the insertion phase of the TL branch. By increasing the number of transmission poles of the BPF branch, the returnloss bandwidth can be increased. Analysis of the BPF topology with one, two, and three transmission poles is provided. The design parameters for 22.5 , 45 , 90 , are provided for bandwidths of 30%, 50%. The three bit digital phase shifter is designed with minimum phase shift of 22.50 and maximum phase provided is 157.50. Results of all three bit phase shifts are produced and their respective phase errors and return losses are compared. | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | TD 807;59 | - |
dc.subject | DIGITAL PHASE SHIFTER | en_US |
dc.subject | PHASE ERROR BANDWIDTH | en_US |
dc.subject | RETURN LOSS BANDWIDTH | en_US |
dc.title | DESIGN OF DIGITAL PHASE SHIFTER WITH VARIOUS ORDERS OF BPF | en_US |
dc.type | Thesis | en_US |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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Ajay Thesis.pdf | 920.38 kB | Adobe PDF | View/Open |
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