DESIGN OF LOW POWER LOW VOLTAGE GILBERT CELL BASED MULTIPLIER CIRCUIT

Abstract

This thesis presents four quadrant analog multiplier circuit using CMOS and NMOS based on the Gilbert Cell multiplier architecture. Both the multipliers operate in saturation region. Analog multipliers are used in communication circuits, neural networks as well as frequency doublers, RMS circuits and phase detectors. High linearity is the prime issue for multipliers in conventional applications like modulation circuits. Initially, different multiplier architectures are reviewed. Multiplier using CMOS and NMOS is designed and simulated. The input power supply for the multipliers is ±1.5V with the input signal range ±10mV. The multiplier circuit is simulated on PSPICE using 180nm technology Level 7 provided by Mosis. The bandwidth of NMOS multiplier is 38.99 GHz and power dissipation is .35mW. The bandwidth of CMOS multiplier is 26.72 GHz and power dissipation is .07255mW.