IMPROVING SIGNAL PROCESSING IN ADCs

Abstract

A current-mode technique for the design of algorithmic ADCs is presented. The current mode technique allows the necessary voltage swing for a given dynamic range to be reduced while at the same time eliminating the need of large capacitors on which to store charge. Consequently the resulting ADC can be made very small and yet still capable of providing high sampling rates. In this thesis the advantages and disadvantages of various current mirror structures used in the ADCs are discussed. Also, the ADCs have been implemented by using different current comparators. For the current-mode ADC, the algorithmic ADC was selected because presently this style of converter occupies the smallest amount of silicon chip area. This architecture also takes the advantage of relatively simple hardware to produce either a Gray-code output or a binary-code output.