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DC Field | Value | Language |
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dc.contributor.author | SARKAR, INDRAJIT | - |
dc.date.accessioned | 2011-04-13T09:56:02Z | - |
dc.date.available | 2011-04-13T09:56:02Z | - |
dc.date.issued | 2006-07-18 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/13599 | - |
dc.description | ME THESIS | en_US |
dc.description.abstract | ield Programmable Gate Array (FPGAs) have emerged as an attractive means of implementing logic circuits providing instant manufacturing turnaround and negligible prototype costs. They hold the promise of replacing much of the VLSI market now held by Mask Programmed Gate Arrays. An important phase in FPGA production is the routing of the cells present inside the arrays for which several CAD tools have been developed. My project is another attempt to implement these routing algorithms which deals with Global and Detailed Routing problems. Two Maze Routing Algorithms-Lee’s and Soukup’s Algorithms and also multilayer maze routing algorithm is studied and implemented. These algorithms are a part of Global Routing phase in the design cycle of an FPGA. In other routing algorithm the spanning tree algorithm is also covered. In Detailed Routing, the channel routing problem, the segmented Channel Routing method has been covered, which in turn consists of Mask Programmed, Fully Segmented, One S... | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | TD 170; | - |
dc.subject | ROUTING | en_US |
dc.subject | VLSI | en_US |
dc.title | IMPLEMENTATION OF VARIOUS ROUTING AND MAZE FOR VLSI ARCHITECTURE | en_US |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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TD-170.pdf | 1.82 MB | Adobe PDF | View/Open |
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