MEMORY ARCHITECTURE DESIGN OF A 32-BIT EMBEDDED PROCESSOR USING VHDL

Abstract

Under this project entitled “Memory Architecture Design of a 32-bit Embedded Processor using VHDL”, the following are modeled using VHDL. 1. A basic 32-bit embedded processor core using VHDL. It uses Register Transfer Level (RTL) description to model the processor. The processor modeled is based on MIPS Architecture. The design uses a 32 bit register file which is an array of thirty two 32-bit registers uses to store data, a 32bit register to store the instruction, 32-bit register to store operational data at various stage, an ALU for arithmetic and logic manipulation and an ALU control which decodes the function to be performed by ALU. Control is implemented using a Finite State Machine model. Multiplexers are used to select from different input signals in each functional blocks. 2. Behavioral model of a 32 bit Random Access Memory with burst transfer protocol implemented 3. Behavioral model of a Direct Mapped Write Through Cache Memory block which utilizes the burst transfer protocol while loading from the Random Access Memory. The simulation is performed using ACTIVE HDL Version 6.3 of ALDEC