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DC Field | Value | Language |
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dc.contributor.author | SHARMA, RAMESH CHANDRA | - |
dc.date.accessioned | 2011-03-03T09:37:24Z | - |
dc.date.available | 2011-03-03T09:37:24Z | - |
dc.date.issued | 2010-11-30 | - |
dc.identifier.uri | http://dspace.dtu.ac.in:8080/jspui/handle/repository/13361 | - |
dc.description | ME THESIS | en_US |
dc.description.abstract | Packaging density of ICs is still following moor’s law but the increasing power consumption levels due to increased number of devices on same die has already become a major concern of the industry. Excessive power dissipation causes overheating, which can lead multiple impacts like, packaging cost, reliability & functionality of IC and other soft errors. This naturally limits battery life of hand held equipments and need urgent solution to enable the proliferation of technology at large. Low-power design methodology, which uses computer-aided design (CAD) capabilities for estimating and optimizing (reducing) the power consumption of designs has been used. In this Project report I have discussed traditional and advanced Low power techniques to save Dynamic as well as leakage powers. I have used Cadence’s Low Power design methodology and tool suit for implementation. | en_US |
dc.language.iso | en | en_US |
dc.relation.ispartofseries | TD712;81 | - |
dc.subject | micron | en_US |
dc.subject | Power | en_US |
dc.title | LOW POWER DESIGN INVESTIGATION OF DEEP SUB-MICRON TECHNOLOGY | en_US |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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MTech-thesis-rameshcsharma-final-1.doc | 3.99 MB | Microsoft Word | View/Open |
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