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Title: | LOW POWER DESIGN INVESTIGATION OF DEEP SUB-MICRON TECHNOLOGY |
Authors: | SHARMA, RAMESH CHANDRA |
Keywords: | micron Power |
Issue Date: | 30-Nov-2010 |
Series/Report no.: | TD712;81 |
Abstract: | Packaging density of ICs is still following moor’s law but the increasing power consumption levels due to increased number of devices on same die has already become a major concern of the industry. Excessive power dissipation causes overheating, which can lead multiple impacts like, packaging cost, reliability & functionality of IC and other soft errors. This naturally limits battery life of hand held equipments and need urgent solution to enable the proliferation of technology at large. Low-power design methodology, which uses computer-aided design (CAD) capabilities for estimating and optimizing (reducing) the power consumption of designs has been used. In this Project report I have discussed traditional and advanced Low power techniques to save Dynamic as well as leakage powers. I have used Cadence’s Low Power design methodology and tool suit for implementation. |
Description: | ME THESIS |
URI: | http://dspace.dtu.ac.in:8080/jspui/handle/repository/13361 |
Appears in Collections: | M.E./M.Tech. Electronics & Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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MTech-thesis-rameshcsharma-final-1.doc | 3.99 MB | Microsoft Word | View/Open |
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