VHDL IMPLEMENTATION AND VERIFICATION OF QUAD DS-1 FRAMER

Abstract

DS-N Digital Signal Hierarchy, A time division multiplexed hierarchy of standard digital signals used in telecommunications systems. DS1 level in the hierarchy corresponds to a 1.544 Mbps TDM signal which comprises 24 DS0 signals. DS0 refers to individual digital signals at channel rates of 64 Kbps. This project is an undertaking to create DS1 framer. The hardware receives the combined output from the 24 voice channels operating at 64 Kbps, assembles it into DS1 frame format. Quad DS1 framer can be logically seen as four DS1 framers working on the same clock. The project has been fully simulated and the results from simulation have been compared to standard DS1 frame.