VERILOG VERIFICATION METHODOLOGY FOR SERIAL PROTOCOLS

Abstract

Serial SCSI (SAS) in a very short duration has become a topic of great interest due to its significant advantages over other competing technologies. The significant increase in SAS products requires stringent techniques to verify the first generation SAS products. Verification IP (VIP) plays an important role in validating the functionality of design, by providing enhanced productivity to the system and by significantly reducing the time to create the verification infrastructure and test bench environment. This Project “Verilog Verification of Serial Protocols” involves design of SAS Monitor and Protocol Checker for the interface between Link layer and PHY (Physical) layer. The SAS Monitor displays the traffic on the bus interface between Link layer and PHY layer. The Checker checks for any protocol violation on bus and flashes any error encountered during transaction. The SAS Monitor and the SAS Checker combined together are independent modules and can be used with any SAS Bus Functio...