VERIFICATION OF CONFIGURABLE IOB ACCORDING TO JEDEC STANDARDS

Abstract

In this thesis Input Output block of FPGA is verified according to JEDEC standards. IOB’s used in FPGA’s are made configurable to support different applications. These IOB comply with electrical standard described by the JEDEC documents. In this thesis the postlay netlist of configurable IOB of FPGA is verified according to JEDEC standard. And the rise to rise delay, fall to fall delay and output duty cycle are also measured. Maximum frequency of operation of IOB was also verified. The simulations were carried out on EDA tools Eldo and Hspice. Measurements were done on the output waveforms. A relationship between rise delay, fall delay, input & output duty cycle was observed. An expression was derived which explains the behaviour observed, & this expression lets us calculate the maximum frequency when output is limited by duty cycle. The theoretical values found by the relation were confirmed with simulation results