| Preview | Issue Date | Title | Author(s) |
| 2023-05 | A COMPARATIVE ANALYSIS AND DESIGN OF DYNAMIC LATCHED COMPARATORS | YADAV, MAHIMA SINGH |
| 2023-05 | FUSION-BASED TECHNIQUES FOR IMAGE DEHAZING | PURKAYASTHA, PAULAMI |
| 2023-05 | PERFORMANCE ANALYSIS OF MEMRISTOR BASED SRAM AND CONVENTIONAL 6T SRAM CELL | SHEKHAR, MAYANK |
| 2023-05 | BIO-INFORMATICS DATA CLASSIFICATION USING KNN ON FPGA BOARD | MANGLA, MAYANK |
| 2023-05 | OPTIMIZING IOT NETWORKS : A GNU RADIO IMPLEMENTATION OF MULTI ARMED BANDITS LEARNING | SEHRAWAT, GAURAV |
| 2023-05 | FORMAL TECHNIQUES TO VERIFY FUNCTIONALITY OF DIGITAL MEMORY DECODER | KASANA, GAURAV |
| 2023-05 | IMPLEMENTATION OF NANOWIRE RECONFIGURABLE FET AS A BIOSENSOR WITH IMPROVED SENSITIVITY | SINGH, DIVYANSH |
| 2023-05 | ACCURATE IMAGE CLASSIFICATION FOR IMPROVED VISION RECOGNITION USING HIERARCHICAL TRANSFER LEARNING | LAL, AKANSHA |
| 2023-05 | STUDY AND DESIGN OF LOW POWER TECHNIQUES FOR CMOS CIRCUITS | BANSAL, ABHAY ANOKHA |
| 2023-05 | VEDIC MATHEMATICS-DRIVEN APPROACH TO HIGH-SPEED AND ENERGY-EFFICIENT ALU DESIGN | SINGH, AMIT |
| 2023-05 | CLASSIFICATION OF EMG SIGNALS OF EYE MOVEMENT USING MACHINE LEARNING TECHNIQUES | SRIVASTAVA, AKSHANSH |
| 2023-05 | POST SILICON FUNCTIONAL VALIDATION : PCLE | SINGH, SURAJ |
| 2023-05 | POWER, PERFORMANCE AND AREA METRICS IN VLSI DESIGN: AN ANALYTICAL APPROACH | MULANI, JUNED ALTAF |
| 2023-05 | DESIGN AND ANALYSIS OF A LOW POWER AND HIGH PERFORMANCE 10T SRAM CELL AT 32 NM TECHNOLOGY NODE | YADAV, PUNEET |
| 2023-05 | PERFORMANCE ANALYSIS OF AN IMPROVED 8T SRAM CELL FOR LOW POWER AND HIGH SPEED APPLICATIONS | USHAM, DEBERJEET |
| 2021-06 | DESIGN OF A NOVEL TERNARY D FLIP-FLOP BASED ON GNRFET | PATHAK, SHASHANK |
| 2021-06 | COMPUTER-ASSISTED SKIN LESION DIAGNOSIS AND MELANOMA CANCER DETECTION | THAKUR, SUNNY |
| 2021-05 | EMBEDDED LINUX FOR HEALTHCARE APPLICATIONS | SAGAR, ISHITA |
| 2021-10 | MICROWAVE LINK PLANNIN & TIME SERIES BASED MICROWAVE LINK CAPACITY OPTIMIZATION | JAHED, MOHAMMAD JAWAD JAHED |
| 2020-06 | COMPARISION OF POWER AND PERFORMANCE OF FULL-ADDER USING DYNAMIC CMOS LOGIC, NORA LOGIC, AND NORA LOGIC WITH MTCMOS OF SUB-45nm TECHNOLOGY NODE | ABHISHEK |
