M.E./M.Tech. Electronics & Communication Engineering
: [710]
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Collection's Items (Sorted by Submit Date in Descending order): 561 to 580 of 710
| Preview | Issue Date | Title | Author(s) |
| - | High performance detection method using memo technology and v-blast architecture | MEENA, RATANDEEP |
| - | Hand Gesture Recognition in Complex Background | SHARMA, RICHA |
| - | MULTIPLE OBJECT TRACKING EMPLOYING OPTIMAL PARAMETRIC ESTIMATION | AJAY KUMAR |
| - | MULTIBAND TRIANGULAR PATCH ANTENNA | Srivastava, Prateek |
| - | CURRENT CONVEYOR BASED VLSI DESIGN | BAGHEL, YOGENDRA SINGH |
| - | DESIGN OF REVERSIBLE LOGIC GATES AND THEIR APPLICATIONS | Rathi, Rounak J |
| - | DESIGN OF ANALOG GILBERT CELL MULTIPLIER USING CMOS TECHNOLOGY | JAGDISH PRASAD |
| - | SPEECH RECOGNITION IN THE PRESENCE OF WIDEBAND NOISE | SAINI, ASHISH KUMAR |
| - | ANALYSIS AND IMPLEMENTATION OF EFFICIENT AUDIO WATERMARKING | SAHU, MUKESH |
| - | OBJECT TRACKING USING PARTICLE FILTER | Yadav, Suman |
| - | OBJECT TRACKING USING PARTICLE FILTER | Yadav, Suman |
| - | ECG Denoising Using The Wavelets And Robust Analysis Of ECG Signals | MUNJAL, NAVEEN KUMAR |
| - | GENERATION AND COMPARISON OF ECG SIGNAL USING MATLAB | SINGH, TARUN PRATAP |
| - | INTRUDER MOTION DETECTION AND RECORDING IN THE REGION OF INTEREST | TOLIA, YOGESWARI |
| 2013-07-11 | Dynamic Power Optimization of 1-Bit CMOS Full Adder Using Genetic Algorithm | SINGH, MEHARBAN |
| 2013-07-11 | Layout Area Optimization of 1-Bit CMOS Full Adder Using Genetic Algorithm | Mayank kumar |
| 2013-07-11 | Low Power Low Voltage Amplifier for removal of offset and Noise | Agarwal, Priyank |
| 2013-07-11 | Design of Current Comparators and its Application as ADC | Sridhar, Ranjana |
| 2013-06-20 | DESIGN OF MICROSTRIP LINE COUPLER WITH IMPROVED DIRECTIVITY | BARTHWAL, AYUSHI |
| 2013-06-20 | ACTIVITY RECOGNITION USING FINITE ELEMENT METHOD | JAIN, MONEY |
Collection's Items (Sorted by Submit Date in Descending order): 561 to 580 of 710
