Collection's Items (Sorted by Submit Date in Descending order): 21 to 40 of 743
| Preview | Issue Date | Title | Author(s) |
| 2026-05 | HYBRID DEEP LEARNING BASED TIMING CHARACTERIZATION OF STANDARD CELL USING SLEW AND LOAD VARIATIONS | ROHIT; INDU, S. (SUPERVISOR) |
| 2026-06 | STATIC CHECKS IN RTL DESIGN : ENSURING CODE QUALITY AND RELIABILITY | PURI, NIKITA; Rewari, Sonam (SUPERVISOR) |
| 2026-05 | NOVEL 13T SRAM CELL DESIGN: IMPROVED NOISE MARGIN & REDUCED DYNAMIC POWER USING 90NM GENERIC PROCESS DESIGN KIT (GPDK) | KUMAR, ARUN; RATRE, AVINASH (SUPERVISOR) |
| 2026-06 | DESIGN OF SINGLE CYCLE 32-BIT RISC-V PROCESSOR | KARTIKE; Gautam, Ajai (SUPERVISOR) |
| 2026-05 | HETERO-DIELECTRIC NANOWIRE FET FOR RADIATION SENSING DOSIMETER APPLICATIONS | TANWAR, KANCHAN; Rewari, Sonam (SUPERVISOR) |
| 2026-05 | DESIGN AND SIMULATION OF A POCKET-ENGINEERED DIELECTRIC-MODULATED TFET BIOSENSOR FOR LABEL-FREE BREAST CANCER DETECTION | BHARGAV, SHISHIR; Kale, Sumit (SUPERVISOR) |
| 2026-05 | POWER INTEGRITY ENHANCEMENT IN ADVANCED ICS USING DECOUPLING CAPACITORS AND POWER GRID OPTIMIZATION | KUMAR, SANTOSH; Indu, S.(SUPERVISOR) |
| 2025-06 | DESIGN AND PERFORMANCE ANALYSIS OF GATE ALL AROUND NANOWIRE FET FOR SUPPRESSION OF SHORT CHANNEL EFFECTS | ROY, SAGAR; Dhariwal, Sachin (SUPERVISOR) |
| 2026-06 | ANALYSIS OF LOW-POWER 2:1 MULTIPLEXERUSING DMLANDLDMLTECHNIQUES | ANAND, NIKITA; NAND, DEVA (SUPERVISOR) |
| 2026-06 | DESIGN OF TERNARY FULL ADDER AND COMPARATOR USING GAA-CNTFET | SINGH, KEERTI; CHAUHAN, ANURAG(SUPERVISOR) |
| 2026-06 | A MILLIMETER-WAVE ANTENNA DESIGN USING METASURFACE TECHNOLOGY FOR 5G APPLICATIONS | KUMAR, GYANESH; Harikesh (SUPERVISOR) |
| 2025-06 | DESIGN AND SIMULATION OF HETERO-JUNCTION TUNNEL FET FOR BIOSENSING APPLICATION | UPADHYAY, SHASHI RANJAN; Kale, Sumit (SUPERVISOR); Pandey, Anukul (CO-SUPERVISOR) |
| 2025-05 | NOVEL SIGNAL-FEED THROUGH FLIP-FLOP OPERATION WITH LOW POWER CONSUMPTION AND HIGH SPEED | VERMA, TUSHANT; Sharma, Yashna (SUPERVISOR) |
| 2025-06 | SIGNAL GENERATION AND PROCESSING APPLICATIONS USING CURRENT MODE BUILDING BLOCKS | PUSHKAR, TVISHA |
| 2025-06 | DESIGN AND COMPARATIVE ANALYSIS OF A DIFFERENT FULL ADDERS FOR LOW POWER AND HIGH-SPEED VLSI APPLICATIONS ACROSS TECHNOLOGY NODES | TALHA, MOHAMMAD |
| 2025-05 | DESIGN OF GATE DIFFUSION INPUT BASED ENERGY EFFICIENT CNTFET CIRCUITS | PARMAR, YASHODA |
| 2025-05 | DESIGN AND PERFORMANCE ANALYSIS OF AN IMPROVED LOW-POWER 8T SRAM CELL FOR ENHANCED WRITABILITY | VISHWAKARMA, AKHILESH |
| 2025-06 | IMPLEMENTATION OF SWITCH DEBOUNCE CIRCUIT USING GDI BASED SCHMITT TRIGGER | SAINI, PRAKHAR |
| 2025-05 | OPTIMIZATION IN CONVENTIONAL COMPOSITE RECESSED STRUCTURED HEMT | SINGH, AASTHA |
| 2025-06 | DESIGN AND IMPLEMENTATION OF LOW POWER ARITHMETIC AND SHIFT REGISTER CIRCUITS USING GDI TECHNIQUE | ROY, AMARTYA |
Collection's Items (Sorted by Submit Date in Descending order): 21 to 40 of 743
