Collection's Items (Sorted by Submit Date in Descending order): 1 to 20 of 730
| Preview | Issue Date | Title | Author(s) |
| 2026-06 | A LOW POWER HIGH VOLTAGE HIGH FREQUENCY PULSER CIRCUIT DESIGN FOR DENTAL APPLICATION | PM, THIVYA SEKHAR; KAPOOR, RAJIV (SUPERVISOR) |
| 2026-06 | AYOLO-BASEDSYSTEMFORREAL-TIME DETECTIONOFDEFECTS INPRINTED CIRCUIT BOARDS | VARMA, GADIRAJU NARENDRA; VERMA, O.P. (SUPERVISOR) |
| 2026-05 | DEEP LEARNING BASED PROPAGATION DELAY PREDICTION AND SENSITIVITY ANALYSIS OF CMOS LOGIC CIRCUITS | NEGI, ANKITA; Suneja, Kriti (SUPERVISOR) |
| 2026-06 | FGMOS BASED VDTA REALIZATIONS WITH ENHANCED PERFORMANCE | SAXENA, ARUSHI; Pandey, Rajeshwari (SUPERVISOR) |
| 2026-06 | A CONFORMAL EBG-INTEGRATED MICROSTRIP PATCH ANTENNA FOR ENHANCED PERFORMANCE AT 2.4 GHZ ISM BAND | RANA, SNEHA; Khandelwal, Sumit Kumar (SUPERVISOR) |
| 2026-05 | SMART ECO FILL FOR FASTER DESIGN CYCLE AND DFM AT DEEP SUB-MICRON TECHNOLOGY | SINGH, MUSKAN; Singh, Alok Kumar (SUPERVISOR) |
| 2026-05 | MEMORY BUILT IN SELF TEST INSERTION IN SOC FOR TESTING AND VALIDATION | SRIVASTAVA, SAHIL; Singh, Kaustubh Ranjan (SUPERVISOR) |
| 2026-05 | HYBRID DEEP LEARNING BASED TIMING CHARACTERIZATION OF STANDARD CELL USING SLEW AND LOAD VARIATIONS | ROHIT; INDU, S. (SUPERVISOR) |
| 2026-06 | STATIC CHECKS IN RTL DESIGN : ENSURING CODE QUALITY AND RELIABILITY | PURI, NIKITA; Rewari, Sonam (SUPERVISOR) |
| 2026-05 | NOVEL 13T SRAM CELL DESIGN: IMPROVED NOISE MARGIN & REDUCED DYNAMIC POWER USING 90NM GENERIC PROCESS DESIGN KIT (GPDK) | KUMAR, ARUN; RATRE, AVINASH (SUPERVISOR) |
| 2026-06 | DESIGN OF SINGLE CYCLE 32-BIT RISC-V PROCESSOR | KARTIKE; Gautam, Ajai (SUPERVISOR) |
| 2026-05 | HETERO-DIELECTRIC NANOWIRE FET FOR RADIATION SENSING DOSIMETER APPLICATIONS | TANWAR, KANCHAN; Rewari, Sonam (SUPERVISOR) |
| 2026-05 | DESIGN AND SIMULATION OF A POCKET-ENGINEERED DIELECTRIC-MODULATED TFET BIOSENSOR FOR LABEL-FREE BREAST CANCER DETECTION | BHARGAV, SHISHIR; Kale, Sumit (SUPERVISOR) |
| 2026-05 | POWER INTEGRITY ENHANCEMENT IN ADVANCED ICS USING DECOUPLING CAPACITORS AND POWER GRID OPTIMIZATION | KUMAR, SANTOSH; Indu, S.(SUPERVISOR) |
| 2025-06 | DESIGN AND PERFORMANCE ANALYSIS OF GATE ALL AROUND NANOWIRE FET FOR SUPPRESSION OF SHORT CHANNEL EFFECTS | ROY, SAGAR; Dhariwal, Sachin (SUPERVISOR) |
| 2026-06 | ANALYSIS OF LOW-POWER 2:1 MULTIPLEXERUSING DMLANDLDMLTECHNIQUES | ANAND, NIKITA; NAND, DEVA (SUPERVISOR) |
| 2026-06 | DESIGN OF TERNARY FULL ADDER AND COMPARATOR USING GAA-CNTFET | SINGH, KEERTI; CHAUHAN, ANURAG(SUPERVISOR) |
| 2026-06 | A MILLIMETER-WAVE ANTENNA DESIGN USING METASURFACE TECHNOLOGY FOR 5G APPLICATIONS | KUMAR, GYANESH; Harikesh (SUPERVISOR) |
| 2025-06 | DESIGN AND SIMULATION OF HETERO-JUNCTION TUNNEL FET FOR BIOSENSING APPLICATION | UPADHYAY, SHASHI RANJAN; Kale, Sumit (SUPERVISOR); Pandey, Anukul (CO-SUPERVISOR) |
| 2025-05 | NOVEL SIGNAL-FEED THROUGH FLIP-FLOP OPERATION WITH LOW POWER CONSUMPTION AND HIGH SPEED | VERMA, TUSHANT; Sharma, Yashna (SUPERVISOR) |
Collection's Items (Sorted by Submit Date in Descending order): 1 to 20 of 730
