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STUDY OF ALTERNATIVE LOGIC STYLES SUITABLE FOR LOW POWER VLSI DESIGN See

ANALYTICAL MODELING, SIMULATION AND CHARACTERIZATION OF JUNCTIONLESS ACCUMULATION MODE MOSFET FOR ANALOG AND RF CIRCUIT APPLICATIONS See

EFFICIENT TECHNIQUES FOR CLASSIFICATION OF MEDICAL IMAGES See

MEDICAL IMAGE ANALYSIS OF WIRELESS CAPSULE ENDOSCOPY DATA See

LOW POWER, DUAL MODE OPERATIONAL 7T SRAM BIT CELL AND SENSE AMPLIFIER FOR PERFORMANCE ENHANCEMENT See

ENHANCED sEMG SIGNALS PROCESS WITH TWO-STREAM CNN ON GESTURE CLASSIFICATION See

LEVERAGING ENSEMBLE LEARNING FOR CLASSIFICATION OF OLD PEOPLE AND KIDS See

SELF TESTING RISC PROCESSOR USING JTAG See

STRATEGIES AND METHODOLOGIES FOR LOW POWER INVERTER DESIGN See

IMAGE DEHAZING: BBHE DSIHE METHOD IN MEDICAL X-RAY IMAGES See

APPLICATIONS OF END TO END AUTOMATIC SPEECH RECOGNITION See

PERFORMANCE EVALUATION OF LOW POWER SRAM CELL See

VISUAL TRANSFORMERS FOR IMAGE UNDERSTANDING See

MACHINE LEARNING BASED ANALOG CIRCUIT DESIGN AUTOMATION See

A 12-Bit 1.2-GS/s CURRENT-STEERING DAC in 45-nm CMOS TECHNOLOGY See

SENSITIVITY INVESTIGATIGATION OF UNDERLAP GATE CAVITY BASED RECONFIGURABLE SILICON NANOWIRE SCHOTTKY BARRIER TRANSISTOR FOR BIOSENSOR APPLICATION See

ROUTER 1x3 RTL DESIGN PACKET BASED PROTOCOL USING VERILOG HDL See

ANALOG CIRCUIT DESIGN OF SPIKING NEURAL NETWORKS See

LOW POWER ISOLATED READ PORT SRAM CELL DESIGN IN 45nm WITH LECTOR TECHNIQUE See

DESIGN AND ANALYSIS OF A 45NM LOW-POWER HIGH-STABLE PROPOSED 8T SRAM CELL AND ARRAY See