DESIGN AND SIMULATION OF 4-BIT COMPARATOR USING DYNAMIC CMOS LOGIC

Abstract

A CMOS Logic 4-Bit Comparator is design using SCL 1.2um technology. The logic diagram is determined to implement the comparator functions less than and equal to and Top-to- Down Full Custom approach is used for the VLSI design flow. The goal of the project is to maximize the performance of the comparator (to achieve high speed). In the designing of CMOS Logic 4-Bit comparator first the VLSI Design Flow chart has been decided. After considering the design specification the Behavior representation, Logic(gate-level)Representation, Circuit Representation and layout representation is done. This process includes VHDL coding, simulation, synthesis, Spice simulation. After all this CMOS Logic is implementer and worst case analysis is done. In last a final layout is drawn on L-edit and area, delay and power is estimated. This is quantified by the worst-case propagation delay of the structure and power. Due to some constraints in Tanner database containing standard cell layouts and also...