“ DESIGN AND IMPLEMENTATION OF TIME SLICED/SHARED SDH TRIBUTARY POINTER PROCESSING AND ALIGNMENT,USING VHDL”

Abstract

Time sliced/shared SDH Tributary Pointer Processor and Alignment design, compensates for the plesiochronous relationship between incoming and outgoing higher level (AU-4) synchronous payload envelope frame rates through processing of the lower level (TU12 or TU3) Tributary pointers. By processing the Tributary pointers with in the SDH frames, it passes the AU level justification into Tributary level justification by adjusting TU pointers and thus it aligns the Tributary columns with in the SDH frame. These aligned tributaries occupy the fixed columns with in the SDH frames. For cross connecting an incoming Tributary Unit (TU) into an outgoing STM-1 stream, One way is to use Time slot Interchange switching (TSI). In TSI switching to maintain a constant data delay in the output lines, irrespective to the position of the time slot in the frame, at least three frames need to be stored. This not only requires a huge memory but also introduce a large delay in the output, which is highly...