DESIGN AND IMPLEMENTATION OF HDLC CONTROLLER IN VHDL

Abstract

HDLC (High-level Data Link Control) is a group of protocols for transmitting synchronous data (Packets) between (Point-to-Point) nodes. In HDLC, data is organized into a frame. HDLC protocol resides with Layer 2 of the OSI model, the data link layer. It is an efficient layer2 protocol standardized by ISO for point-to-point and multipoint data links. HDLC provides minimal overhead to ensure flow control, error control, detection and recovery for serial transmission. In this thesis a simple HDLC Controller has been designed, implemented and tested. This chip is targeted to be implemented on Field programmable gate array (FPGA) or complex programmable logic device (CPLD). This is then coded in a very high speed integrated circuits (VHISC) hardware description language (VHDL). The functioning of the coded design has been simulated on simulation tool (e.g. ModelSim SE-EE 5.4a). After functional simulation, the design has been synthesized and then translated to a structural architectu...