DESIGN AND IMPLEMENTATION OF DATA ENCRYPTION STANDARD USING VHDL

Abstract

Many people wish to communicate privately. To prevent unauthorized persons from extracting information from the communication channel or injecting misinformation into the communication channel, messages need to be disguised by encryption. At the transmitter, the plaintext is encrypted to produce the ciphertext. The ciphertext is transmitted over an insecure channel to the receiver. The receiver then decrypts the ciphertext to obtain the original plaintext. DES, which stands for Data Encryption Standard is a block encryption algorithm adopted by the National Bureau of Standards. With this algorithm, a 64-bit plaintext and a 64-bit key are provided as input. By applying a sequence of initial permutation, switch, shift on the key and plaintext, the 64-bit ciphertext is generated at the output after 16 clock cycles. A test bench for simulation is critically important for the final success of the whole work. This test bench provides a sequence of key and plaintext to the DES design. With the test bench, the pre-synthesis simulation is then made using Active HDL 6.3. This is an RTL level simulation which verifies the logic functionality of the code without gatelevel information involved. After the successful pre-synthesis simulation, IDE Xyling Project Navigator is used to synthesize the DES design. The main objective of the project is to design a synthesizable VHDL model for Data Encryption Standard Algorithm.The basic idea behind a synthesizable model is the need to implement the algorithm on FPGA.Implementing cryptographic algorithm on reconfigurable hardware provides major benefits over VLSI and software platforms since they offer high speed similar to VLSI and high flexibility similar to software.