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DESIGN AND ANALYSIS OF GAIN ENHANCED MICROSTRIP ANTENNAS USING METAMATERIALS FOR 5G APPLICATIONS

2026-04-01T00:00:00Z

Title: DESIGN AND ANALYSIS OF GAIN ENHANCED MICROSTRIP ANTENNAS USING METAMATERIALS FOR 5G APPLICATIONS Authors: KHANDEKAR, ROHIT SURESH; Sipal, Deepika (SUPERVISOR) Abstract: The surge in demand for high data rates has resulted in the exponential growth of wireless communication systems. Thus, there is a requirement for compact, high gain, and Wideband/ Ultra-wideband (UWB) antennas capable of supporting 5G and beyond communication networks has also increased exponentially. With increasing reliance on high data rates, wide impedance bandwidths (BW), Low-latency, and seamless connectivity, antenna systems must evolve to address challenges such as spectrum congestion, gain enhancement, polarisation control, and size reduction. The antenna parameters, such as Gain, Directivity, BW, Polarisation, Radiation Patterns and Efficiency, can be ‘enhanced’ by introducing the Metamaterials (MMTs)/ Metasurfaces (MSs). This thesis presents an in-depth investigation into the design and analysis of gain enhanced microstrip antennas using MTMs/ MSs, and 3D-printed Metastructures. The research is focused on Sub-6 GHz, X-band, and millimetre-Wave (mm-Wave) frequency ranges, covering applications in Internet of Things (IoT), Internet of Vehicles (IoV), CubeSat systems, point-to-point (p2p) terrestrial 5G communication, and Small 5G Base stations. In the Sub-6 GHz band, a UWB Multiple Input Multiple Output (MIMO) antenna is designed to achieve a wide impedance BW of 2.37 GHz to 8 GHz with a fractional BW of 108.58%. The antenna, intended for IoT/IoV applications, integrates an artificial magnetic conductor (AMC) with dual rings to generate dual resonances, enhancing gain and improving port isolation. The 5 × 8 AMC array placement enhances gain up to 7 dBi from a baseline of 2.3 dBi, while isolation is improved to >19.66 dB. Furthermore, essential MIMO performance metrics such as ECC (<0.0037), CCL (<0.12 bits/s/Hz), and TARC (< -10 dB) remain within acceptable limits. The compact size and wide operational BW of the design make it suitable for IoT, WiFi, LTE, WiMAX, and WiFi-6E bands. For CubeSat applications, a circularly polarised (CP) antenna is proposed using a polarisation reconfigurable metasurface (PRMS). By forming a Fabry–Perot cavity with a 9 × 9 PRMS array, the antenna achieves an Axial Ratio BW (ARBW) of 2.31 GHz, closely matched with an impedance BW of 2.41 GHz. The design enhances the gain from 7.3 dBi to 17.1 dBi while achieving compatibility with both right-hand and left-hand CP waves. This antenna design addresses one of the critical challenges in CP antenna design, where ARBW is typically narrower than impedance BW, thereby making the antenna suitable for satellite based communication. In the X-band spectrum, a phase gradient metasurface flat lens (PGMS-FL) is introduced to attain a high gain, narrow beams for p2p terrestrial 5G communication. The PGMS-FL array achieves beamwidths between 13.2° and 16.5° with a maximum gain of 17.7 dBi at 11.2 GHz. The polarisation-insensitive nature of the PGMS unit cells ensures ± ` viii stable CP performance, making the antenna a viable candidate for terrestrial p2p 5G communication. Four distinct antennas are designed and analysed at mm-Wave frequencies to overcome propagation losses and achieve high capacity wireless links. A UWB AMC array is used to enhance the gain of a MIMO antenna from 8.5 dBi to 12.21 dBi while maintaining port isolation above 19 dB. A second MIMO antenna, integrates a PGMS lens for beam tilting to ± 24º, enabling robust non-line-of-sight (NLOS) communication to improve SNR. The third design incorporates double-negative (DNG) unit cells to achieve a gain improvement of 4 dB and a front-to-back ratio increase from 10.81 dB to 20.6 dB, enhancing link reliability. Finally, a 3D-printed metastructure array embedded in a planar dipole antenna achieves flat gain with 0.45 dB variance, i.e. 11.07 dBi to 11.45 dBi across 22 GHz to 26.6 GHz. The findings of this thesis emphasise the importance of unit cell design in gain enhancement, BW widening, and polarisation stability. On the other hand, Symmetry of the MMT/MS structure, polarisation insensitivity, and angular stability emerge as key factors for optimising metastructures for antenna applications. Integrating AMCs, PRMS, PGMS, DNGs, and 3D-printed metastructures with the different antennas across multiple frequency bands demonstrates significant gain enhancements while maintaining compact profiles. Overall, the research outcomes provide compact, high-performance antenna designs suitable for 5G communication. The proposed antennas cover diverse frequency bands, which include WiFi/ WiMAX/ Bluetooth, Mid-band, Sub-6 GHz, WiFi-6E X- band, MVDDS, and mm-Wave band, enabling its applications in IoT/IoV, terrestrial 5G networks, CubeSat communication, and broadband satellite services. By addressing challenges such as narrow BW, low gain, polarisation mismatching, and size, this thesis contributes to the advancement of antenna designs that are efficient, reliable, and adaptable to the evolving needs of modern communication systems. The major highlights of this research are: • Design antennas to cover newly defined frequencies by the FCC (WiFi-6E and MVDDS) with an enhanced gain. • To enhance the ARBW of the CP antenna and increase the gain using MMT or a metal cavity, with a small structure. • Design an antenna with gain enhancement for wide impedance BW, low profile and high directivity. • To achieve gain enhancement for UWB antennas, maintaining antenna size as minimal as possible. • Design an electrically small antenna with flat gain through the operating BW and a high front-to-back ratio.

DESIGN AND PERFORMANCE ANALYSIS OF SAR ADC FOR LOW POWER APPLICATIONS

2026-04-01T00:00:00Z

Title: DESIGN AND PERFORMANCE ANALYSIS OF SAR ADC FOR LOW POWER APPLICATIONS Authors: TYAGI, MOHIT; Mittal, Poornima (SUPERVISOR); Kumar, Parvin (CO-SUPERVISOR) Abstract: Analog to Digital Converter (ADC) is an important module in the analog front end system that exists between sensors and digital signal processing block. Different architectures of ADCs like Flash, Pipelined, Delta Sigma and Successive Approximation Register (SAR) exist in literature that are utilized for digitization of an analog signal. Moreover, parameters like power consumption, resolution, area, and design cost are considered for the comparison between different existing ADC architectures. Literature indicates that for medium resolution and medium speed applications at low power consumption, SAR ADC is the most suitable choice due to its predominantly digital architecture. In view of these considerations, design of an ultra- low power SAR ADC is undertaken in this research work. A SAR ADC consists of three primary modules: a low-power dynamic comparator, a capacitor- based digital-to-analog converter (CDAC), and a control logic unit that governs the successive approximation process to convert the sampled analog input into its corresponding digital representation. Power consumption of each and every module is required to be reduced so as to reduce the power of complete designed ADC. However, DAC is the most power consuming block in a SAR ADC, design and parametric optimization of each and every module is considered stepwise. First of all, design and parametric simulation analysis of different low power dynamic comparators in CADENCE Virtuoso 45 nm technology node is carried out. In this, Strong arm latch dynamic comparator is considered as the baseline comparator consisting of preamplifier and regeneration latch. This comparator retains the direct path connection between VDD and ground and due to this, the circuit consumes 51.38 nW of average transient power consumption. Further, double tail dynamic comparator and modified double tail dynamic comparator are considered for design, simulation & analysis and the transient analysis of both comparators is focussed. The observed delay, power consumption and kickback noise in these comparators required an architectural improvement in the design of existing comparators. Following this, first proposed dynamic comparator architecture design along with the simulation analysis is focussed. Simulation of first proposed dynamic comparator observed average transient power of 33.81 nW at nn corner which is much reduced value compared to the other architectures like strong arm latch, double tail dynamic and modified double tail dynamic comparator. The power consumption is limited to 19.56 nW at ss corner as the architecture created an isolation between pre-amplifier and latch module when clk is low due to which leakage power is avoided. The vii proposed comparator is simulated with capacitive loading of 5.1 pF which is the required value for utilizing the designed comparator module along with capacitive DAC. PDP of 0.4 fJ along with temperature variation from -40-degree centigrades to 110-degree centigrades is also measured for the first proposed comparator. Further, a dynamic comparator based on charge sharing logic and kickback noise reduction logic is also proposed which is working well for few GS/s and power consumption of 9.36 μW is observed at 1 GS/s. Proposed charge sharing logic based dynamic comparator is limiting offset voltage to 7.8 mV and delay within 48.2 ps. Proposed charge sharing logic-based circuit is less sensitive to Vcm variations as gm/ID of input transistors is enhanced with the biasing of transistors in weak inversion region. The observed delay exhibits a reduction from 56.3 ps to 23.17 ps as the input differential voltage (Vdiff) ranges from 10 mV to 200 mV for varying common-mode voltage levels (Vcm) in the proposed charge sharing dynamic comparator. The comparator demonstrated the reduction in kickback noise by employing auxiliary transistors M8 and M9 (Fig.3.12) to separate the output nodes. Additionally, this approach effectively mitigated the mismatch effect and minimized the impact of parasitic capacitance associated with the transistor design. Further, designing of DAC module with reduced switching energy per conversion step drew attention of researchers in the design of ultra-low power SAR ADC. In literature many DAC switching schemes are implemented by the researchers like common mode switching scheme, monotonic switching scheme, capacitor splitted switching scheme, merged capacitor etc. Each switching scheme followed a different switching methodology and contributed to the saving of switching energy per conversion cycle compared to the conventional one. Traditional switching scheme consume 682.5 CV2ref while 427.66 CV2ref of switching energy is consumed by split capacitor technique. So, there exists a research scope in the design of DAC unit with zero switching energy in the first two MSB comparisons. In view of above, inclusion of single ended topology-based switching scheme for the design of digital to analog converter (DAC) is considered. The proposed switching scheme utilized a single reference voltage of Vref/2 and performed the first two MSB comparisons with zero switching energy. The scheme required average of 57.4 CV2ref of switching energy which is a much-reduced value, approximately reduced by a factor of 92 percent compared to conventional capacitor-based switching scheme. Also, compared to conventional switching scheme, the number of capacitors in the DAC array are reduced by 50 percent. viii In the switching scheme, a single ended behaviour is obtained utilizing a dummy DAC at the positive input of comparator that felicitated first two comparisons without any switching power. Also, after first comparison of Vin with Vref/2, the bottom plate of dummy DAC is switched either to ground or Vref/2 and stayed in that state till the final digitization is performed with Vref value of 1.1 V. Also, for the proposed DAC implementation, MOM capacitors are suggested to be the preferred choice to shift the design from schematic to final back-end stage. Third Module of SAR ADC is the design of a low power control unit. The literature observed the necessity of SAR logic and DAC co-optimization, especially when advanced switching techniques such as monotonic, common-mode (VCM)-based, and capacitor-splitting schemes are employed for switching. Based on the above requirement to design a SAR logic-based control unit with better DAC-logic synchronization and to further reduce nonlinearity in SAR ADC, the design of low power SAR logic-based control unit is considered as further part of the research work. The design of the control unit began with the development of enhanced D flip-flops to improve setup and hold time performance. After this, the clocking system is designed using the main clock along with internally generated clock signals to achieve proper timing synchronization. In the initial stage, multiplexers and sampling logic are implemented to support accurate sampling and signal control. The SAR logic is then generated step by step in a bitwise manner to implement the proposed switching scheme. Finally, by using enhanced D flip-flops and multiplexers with proper synchronization, an improved control unit is developed to successfully implement the proposed switching scheme. Enhanced D flip flop is working well for the required bandwidth and resolution of input signal at low power consumption. The proposed synchronous control unit has less complexity and better timing synchronizations due to which all the control signals are getting generated within time constraints. Sampling phase begins the digitization process when Xs is low and Dp (comparator output) is the digitized output bit which is generating digital data in synchronization with internal generated clock signals (Q1 to Q7) and providing better linearity in the digital data generation process. The control unit implemented the SAR logic in a bitwise manner. After the initial sampling operation triggered by the first clock signal (clkc), the most significant bit (MSB) is resolved. Subsequently, the internal clock signal Q1 provides precise timing synchronization for the generation of the MSB-1 bit. The remaining bits are generated sequentially by the control unit with optimized timing coordination between the DAC and the comparator, thereby improving conversion accuracy. In this process, the internal clock signal Q2 synchronizes the generation of the MSB-2 bit, and the same sequence continued for the ix lower-order bits. The resolved digital bits are stored in a shift register, and based on the clock timing, the stored data is finally read out as an 8-bit digital output of the designed SAR ADC. Proper interfacing of the designed modules along with effective control of the common-mode Vcm is critical for achieving an ultra-low-power SAR ADC. In this work, non-linearities such as differential non-linearity (DNL) and integral non-linearity (INL) are minimized while maintaining low power consumption, in line with observations reported in the literature. The effectiveness of the proposed approach is reflected in the calculated INL and DNL values obtained from the digitized output. Based on these considerations, a fully interfaced 8-bit SAR ADC incorporating all optimized modules is designed. Henceforth, finally, all the designed modules; comparator, DAC & control unit are interfaced to design an 8-bit SAR ADC with single reference voltage Vr/2 based dummy DAC designed along with bootstrap switch to give zero switching energy in first two MSB conversions. The reduced power consumption of the designed 8-bit SAR ADC is limited to the value of 5.38 μW. Parametric simulation analysis shows that SNDR value of 46.08 dB, SFDR 47.89 dB, ENOB 7.38 bits, DNL +0.13/(-0.12) LSB, INL +0.52/(-0.90) LSB at sampling rate of 540 KS/s is obtained. The entire design is simulated in CADENCE 45 nm technology node. The Proposed SAR ADC is completely designed at transistor level implementation of each module including comparator, DAC unit and control logic. The DAC unit consumes zero switching energy in the first two MSB decisions as per proposed switching algorithm which results in the saving of 92 % of switching energy with respect to the conventional switching scheme at 540 KS/s. The research conducted herein shows that the proposed 8-bit SAR ADC is digitizing the analog sampled value in 8 bits with sampling frequency of the order 540 KS/s. The measured parameters validating that power consumption of the designed ADC is limited to 5.38 μW and other parameters like INL, DNL are also within permissible range to confirm the effectiveness of the design for low power sensor applications. The research widens the horizon to include adaptive decision algorithms in the design that can help mitigate non-idealities such as capacitor mismatch and comparator offset in further research.

DESIGN AND ANALYSIS OF PHOTONIC CRYSTAL FIBER FOR SENSING APPLICATIONS

2026-03-01T00:00:00Z

Title: DESIGN AND ANALYSIS OF PHOTONIC CRYSTAL FIBER FOR SENSING APPLICATIONS Authors: CHAUDHARY, VISHAL; SINGH, SONAL (SUPERVISOR) Abstract: Over the past few years, photonic crystal fibers (PCFs) have emerged as a promising class of optical fibers, offering immense potential across a wide range of applications, particularly in telecommunications and sensing technologies. Initially, research on PCFs was mainly focused on enhancing key optical characteristics such as dispersion, nonlinearity, confinement losses, and birefringence. However, with ongoing advancements in fiber fabrication techniques, PCF-based sensors have gained increasing attention, especially in the domain of sensing. A notable development in this field is the rapid progress of surface plasmon resonance (SPR)-based sensing technologies. Traditional prism-based SPR sensors, known for their label-free detection and real-time monitoring capabilities, are becoming less favorable due to limitations such as low sensitivity, bulky configurations, and high manufacturing costs. In response, PCF-based sensors have been introduced as a more efficient alternative, offering compact design and improved performance while eliminating the need for extensive experimental setups. This thesis explores the design and analysis of PCF-based sensors tailored for both physical and biological sensing applications. By carefully optimizing the structural parameters of the PCF-based refractive index (RI) sensor, it is possible to achieve high sensitivity, a broad sensing range, and simplified fabrication processes. This thesis begins by providing a concise overview of the development of fiber-optic sensors. Optical fibers serve as effective sensing elements by continuously monitoring variations in the surrounding analyte. While traditional optical fibers are applicable for SPR sensing, their structural and optical limitations hinder further advancement in this area. To overcome these challenges, PCFs have been introduced an innovative class of fibers that integrate the benefits of both optical fibers and photonic crystals. PCFs exhibit unique features that surpass the capabilities of conventional fibers. Among their many applications, PCF-based RI sensors have shown remarkable adaptability in diverse sensing domains, including physical, biological, and chemical detection. The following chapter presents a comprehensive literature review on PCF-based RI sensors for physical and biomedical applications. The review begins with an overview of the fundamental concepts, including mode coupling theory, birefringence, and wavelength sensitivity. It then provides a concise explanation of the suitability of PCFs for RI-based sensing applications, followed by an in-depth discussion on PCF-based SPR sensors. Key areas covered in the discussion include temperature monitoring, analysis of blood components, malaria detection, and sensing of various fluid analytes. The next chapter examines a circular-shaped hollow-core PCF filled with ethanol. The study focuses on analyzing key optical properties such as dispersion, effective mode area, confinement loss, and nonlinear coefficient across a wavelength range of 800 nm to 1600 nm. The primary objective is to attain a near-zero dispersion wavelength (ZDW) using the finite element method (FEM). By varying the filling configuration, air in the entire ring, ethanol in the central ring, and ethanol in the entire ring, ZDW values of approximately 880 nm, 1220 nm, and 1250 nm are achieved, ix respectively. This type of PCF holds significant potential for applications in sensing, nonlinear optics, laser systems, and telecommunications. The following chapter presents a detailed study of a twin-core photonic crystal fiber (TC-PCF) structure designed for temperature and chemical sensing applications. The proposed design features two solid cores separated by a vertically aligned elliptical air hole, which allows for independent light propagation in each core and results in high birefringence. The sensing mechanism is based on mode coupling between the two cores, which significantly enhances sensitivity. The performance of the TC-PCF sensor has been evaluated through simulations using the FEM. The findings demonstrate the sensor's high sensitivity and its suitability for both temperature and chemical detection. Numerical simulations reveal that the 3 cm long TC-PCF sensor has been optimized to exhibit a high temperature sensitivity of approximately 21.5 pm/°C across a broad temperature range of 0 to 1200 °C. Additionally, for chemical sensing, a sensor with a fiber length of just 0.03 cm achieves a maximum sensitivity of 6667 nm/RIU. This chapter covers the theoretical background, structural design, and performance analysis, emphasizing the real-world applicability of TC-PCF-based sensors. Next chapter focuses on the design and investigation of advanced biosensing methods utilizing PCFs for the early identification of a range of diseases, such as multiple forms of cancer, essential blood constituents, and malaria. The research employs FEM simulations conducted in the terahertz (THz) frequency range to analyze mode coupling behaviour in TC-PCF structures, aiming to achieve superior sensitivity and accuracy in biomedical sensing applications. By thoroughly examining key design parameters of PCF, the proposed sensors demonstrate exceptional sensitivity and performance in identifying diseases, thereby supporting progress in biomedical diagnostics and enhancing healthcare technologies. The following chapter introduces a SPR-based PCF sensor specifically designed for the detection of diabetes. Gold is employed as the plasmonic material and is incorporated in a layered structure to enhance the sensor’s overall performance. The design is analyzed using FEM simulations to assess its capability in identifying diabetic conditions. In this sensor configuration, two concentric layers of air holes are organized in a hexagonal lattice, and a thin layer of gold is coated onto the fiber to enable the excitation of the SPR effect. This effect arises when the surface plasmon polariton (SPP) mode interacts with the core-guided mode under phase-matching conditions. Diabetes-related samples, each characterized by a distinct RI, are introduced into the fiber structure. Variations in RI between normal and diabetes-affected samples cause a measurable shift in the SPR resonance wavelength during confinement loss analysis. The sensor achieves a sensitivity of 2400 nm/RIU, as determined by tracking changes in the loss spectrum. With its simple sensing approach, the proposed SPR-PCF sensor offers a practical and cost-efficient solution for diabetes monitoring.

STUDY AND DESIGN OF LOW LEAKAGE NANOWIRE FIELD EFFECT TRANSISTOR

2026-03-01T00:00:00Z

Title: STUDY AND DESIGN OF LOW LEAKAGE NANOWIRE FIELD EFFECT TRANSISTOR Authors: KAUL, AAPURVA; REWARI, SONAM (SUPERVISOR); NAND, DEVA (JOINT SUPERVISOR) Abstract: The continuous downscaling of semiconductor devices, as predicted by the Moore’s law, has significantly improved computational capability, power efficiency and integration density over the past five decades. However, with the transition into the deep sub-nanometer regime, conventional CMOS technology has encountered formidable challenges such as increased leakage currents, degraded subthreshold swing, escalating power dissipation and short channel effects (SCEs). The inability of traditional transistor architectures to maintain electrostatic integrity at reduced dimensions has motivated the exploration of novel device geometries and materials capable of sustaining high performance while ensuring low-power operation. In this context, the present research investigates the design, modelling and performance evaluation of advanced nanowire field effect transistors (FETs) that combine dielectric, ferroelectric and electrostatic engineering to overcome the limitations of conventional MOSFETs. The study is centred on the progressive development of five distinct nanowire FET architectures, each addressing specific challenges of device scaling through geometric and material innovation. The overarching objective of this work is to achieve superior gate controllability, enhanced current drivability and reduced subthreshold swing, thereby paving the way for energyefficient transistors suitable for next-generation nanoelectronics applications. The initial part of the research presents the Double Metal Gate Macaroni Nanowire Field Effect Transistor (DMGM-NFET), where two metals with different work functions are used within the gate stack to modulate the channel potential. This configuration enables a stepwise potential distribution that effectively reduces gate induced drain leakage (GIDL) and drain induced barrier lowering (DIBL). The macaroni type hollow nanowire geometry further enhances gate coupling, allowing improved electrostatic control over the channel region. Simulation results confirm a substantial improvement in subthreshold swing and ON/OFF current ratio when compared to the conventional FETs. This device establishes the foundation for electrostatic optimization through multi metal gating. Building upon this concept, the study extends to the Hetero-Dielectric Macaroni Channel Cylindrical Gate All Around Field Effect Transistor (HD-MC CGAA FET), which employs a dual-dielectric gate stack consisting of high-κ (HfO2) and low-κ (SiO2) materials. The heterogeneous dielectric configuration redistributes the gate electric field, enhancing potential control near the source end while minimizing fringing field effects at the drain. This selective field enhancement results in reduced subthreshold slope and improved channel confinement. Comparative analysis with single-dielectric and single-metal counterparts demonstrates that the hero-dielectric approach yields higher transconductance, improved current and stringer immunity to short channel effects. These findings confirm that dielectric heterogeneity, combined with cylindrical symmetry, can significantly improve device performance at nanoscale dimensions. xi The research then transistors from electrostatic to material-based innovation through the incorporation of ferroelectric materials in the gate stack. The Negative Capacitance Nanowire FET (NC-NW FET) introduces a ferroelectric HfZrO2 layer in series with a high-κ dielectric, harnessing the negative capacitance (NC) effect to achieve internal voltage amplification. This phenomenon allows the device to operate with a subthreshold swing below the Boltzmann limit of 60 mV/decade, leading to lower operating voltages and energy efficient switching. The simulation analysis confirms a marked reduction in power dissipation and a significant improvement in drive current. Furthermore, the hysteresis behaviour is optimized through careful tuning of the ferroelectric layer thickness and capacitance matching with the underlying dielectric stack. The results validate that ferroelectric integration can effectively address the fundamental trade-off between switching speed and power consumption in nanoscale transistors. To further enhance device controllability and eliminate residual instability, the work explores cylindrical ferroelectric architectures, resulting in the Cylindrical Ferroelectric Dual Metal Nanowire FET (C-FE-DM-NW FET). This design combines the advantages of dual metal configuration allows precise control of the potential barrier near the source and drain, while the ferroelectric layer enhances surface potential modulation through polarization-driven voltage amplification. The resulting device exhibits a subthreshold swing below 55 mV/decade, negligible DIBL, and an ON/OFF current ration in the range of 108 -109 , confirming excellent electrostatic integrity. Moreover, the transconductance and drain current are significantly improved, validating that the synergy of dual-metal and ferroelectric gate engineering is crucial for achieving both steep-slope and high-drive devices. The final and most advanced device proposed in this work is the Cylindrical Gate Engineered Ferroelectric Nanowire FET (CGEF-NW FET). This architecture introduces gate-length partitioning and optimized ferroelectric layer placement within the cylindrical structure to achieve near-ideal electrostatic control and hysteresis free operation. The CGEF-NW FET demonstrates an exceptionally low subthreshold swing of approximately 50 mV/decade, a high ON/OFF current ratio exceeding 109 , and minimal power dissipation. The optimization of gate geometry and ferroelectric parameters allows superior potential modulation while maintaining capacitance stability, thereby providing the most balanced performance among all proposed designs. The CGEF-NW FET thus represents the culmination of this research efforts combining geometry, field and material engineering to achieve a scalable and energy efficient transistor for sub-5 nm technology nodes. A comprehensive comparative analysis among all the proposed devices illustrates a clear performance improvement trend: the subthreshold swing decreases from approximately 70 mV/decade in the DMGM-NFET to nearly 50 mV/decade in CGEF-NW FET, while the ON/OFF current ratio increases by more than three orders of magnitude. The DIBL is reduced to nearly negligible levels in ferroelectric devices, and the drain current performance is significantly enhanced. These improvements are attributed to the synergistic interplay between electrostatic optimization, dielectric engineering and ferroelectrics voltage amplification, confirming that the strategic integration of these techniques can collectively surpass the scaling limitations of xii conventional CMOS transistors. The thesis also discusses the future research prospects and practical realization pathways for the proposed devices. Experimental fabrication using Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD) is recommended for producing high-quality HfO2 and HfZrO2 films with nanometre-scale precision. Structural and phase characterization through Transmission Electron Microscopy (TEM) and X0Ray Diffraction (XRD) will enable validation of the simulated results, while Piezo response Force Microscopy (PFM) can be employed to verify ferroelectric polarization and stability. Further optimization of doped ferroelectric materials could improve endurance and minimize coercive voltage, making these designs more robust for integrated circuit applications. The proposed devices are also highly promising for circuit-level and systemlevel integration, particularly in low-power digital logic, non-volatile memory and neuromorphic computing architectures. Their ability to operate at low supply voltages and high switching speeds positions them as potential enablers for energy-efficient processors, artificial intelligence hardware, and edge computing systems. Additionally, due to their low energy consumption and compact footprint, these devices could be extended to flexible electronics and biomedical sensor platforms, paving the way for green and sustainable nanoelectronics systems. From a broader perspective, the innovations presented in this thesis hold substantial technological and societal impact. By significantly reducing the power requirements of electronic systems, the proposed nanowire FETs contribute to global efforts toward energy conservation and sustainable electronics manufacturing. Their compatibility with existing CMOS fabrication processes ensures a practical transition path for semiconductor industries towards post-CMOS device paradigms. Furthermore, the reduction in energy consumption directly aligns with global objectives such as carbon footprint minimization and sustainable digital transformation. In conclusion, this thesis provides a comprehensive and systematic exploration of next-generation nanowire transistor architectures that transcend conventional scaling barriers through a combination of electrostatic design and ferroelectric innovation. The research demonstrates that by co-optimizing gate geometry, dielectric heterogeneity, and ferroelectric polarization, it is possible to achieve sub thermal switching, low leakage, and exceptional electrostatic control all within a CMOS compatible framework. The proposed devices collectively form a technologically feasible and environmentally sustainable foundation for the development of ultrascaled, low power, and high-performance electronics in the post-CMOS era. This work not only advances the scientific understanding of ferroelectric and nanowire device physics but also contributes meaningfully to the realization of energyefficient semiconductor technologies that align with both industrial evolution and societal responsibility.