http://dspace.dtu.ac.in:8080/jspui/handle/123456789/84 2026-04-28T04:03:25Z http://dspace.dtu.ac.in:8080/jspui/handle/repository/22643 Title: SIGNAL GENERATION AND PROCESSING APPLICATIONS USING CURRENT MODE BUILDING BLOCKS Authors: PUSHKAR, TVISHA Abstract: This thesis presents a comprehensive study on signal generation and processing using current-mode active building blocks (ABBs), specifically focusing on the Universal Voltage Conveyor (UVC) and the Voltage Differencing Buffered Amplifier (VDBA). These elements represent a significant advancement in analog signal processing, offering improved performance in speed, linearity, power efficiency, and CMOS compatibility over traditional voltage-mode circuits. The work addresses key bottlenecks in existing oscillator and filter designs by developing novel circuit architectures that are compact, low-power, and capable of robust and tunable operation under practical non-idealities. The research is structured in four parts. The first part introduces the foundational principles of analog signal processing and the advantages of current-mode operation. It also presents a literature review on the evolution and applications of UVC and VDBA, identifying gaps in tuning flexibility, harmonic distortion, and sensitivity to component variations. Particular attention is given to the third-order quadrature sinusoidal oscillator (TOQSO) and multiple-input single-output (MISO) universal filter designs. The second part of the thesis proposes two innovative circuits: an improved TOQSO using UVC and a compact, electronically tunable MISO universal filter using VDBA. The proposed TOQSO achieves independent control over the frequency of oscillation (FO) and condition of oscillation (CO), reducing total harmonic distortion (THD) to below 1.5%, a marked improvement over existing OTA- and CCII-based designs. The MISO filter, designed using a single VDBA, two grounded capacitors, and one resistor, realizes all five second-order filter responses (low-pass, high-pass, band-pass, band-reject, and all- vii pass) without the need for reconfiguration. Both circuits exploit the strengths of their respective ABBs to address the shortcomings of earlier designs. In the third part, rigorous mathematical modeling is presented for both circuits, followed by detailed sensitivity analysis that confirms the low dependence of key parameters (ω₀ and Q) on passive component variations. SPICE simulations using 0.18 μm CMOS technology validate the theoretical predictions. For the TOQSO, output waveforms, frequency spectra, and Lissajous patterns confirm sinusoidal oscillation with quadrature phase accuracy and spectral purity. For the MISO filter, frequency response plots for each mode demonstrate accurate cutoff and center frequencies. Simulation results align closely with analytical derivations. To bridge the gap between simulation and real-world applicability, experimental prototypes of both designs were implemented using commercially available ICs. The TOQSO exhibited stable sinusoidal outputs with precise 90° phase difference, and the filter achieved consistent performance across a frequency range from 10.5 kHz to 500.5 kHz. These results confirm the feasibility and robustness of the proposed circuits under practical conditions, including non-idealities such as voltage tracking errors and finite transconductance mismatches. A comparative performance analysis against conventional designs—OTA-, CCII-, and CDBA-based—demonstrates the superiority of the proposed solutions in terms of spectral purity, power efficiency, component count, and CMOS integration readiness. The VDBA- based filter exhibits lower power consumption and higher Q-factor than its counterparts, while the UVC-based oscillator outperforms in frequency stability and THD. The thesis concludes by outlining the broader implications of these findings. The proposed designs contribute to the advancement of low-voltage, low-power analog front-end systems, particularly in wearable biomedical devices, adaptive communication systems, sensor interfaces, and energy-constrained IoT nodes. Their compactness and simplicity make them ideal candidates for integration into modern VLSI systems. viii Future directions for research include extending these architectures for fully electronically tunable operation, deploying them in multi-band or reconfigurable systems, and implementing them in deep-submicron or emerging device technologies such as FinFETs and CNTFETs. Furthermore, integrating these circuits into system-on-chip (SoC) solutions for biomedical and communication applications could significantly enhance performance and miniaturization. Through its dual focus on theoretical rigor and practical validation, this thesis contributes to the evolving landscape of analog signal processing, establishing reliable and efficient building blocks for next-generation analog integrated circuits. 2025-06-01T00:00:00Z http://dspace.dtu.ac.in:8080/jspui/handle/repository/22642 Title: DESIGN AND COMPARATIVE ANALYSIS OF A DIFFERENT FULL ADDERS FOR LOW POWER AND HIGH-SPEED VLSI APPLICATIONS ACROSS TECHNOLOGY NODES Authors: TALHA, MOHAMMAD Abstract: With the continued scaling of CMOS technology into deep submicron regions, achiev- ing a balance between low power consumption and high-speed operation has become essential in digital arithmetic units. The full adder, a fundamental building block in arithmetic logic units (ALUs), has been widely studied to reduce power, delay, and area metrics. Traditional 28-transistor (28T) and 14-transistor (14T) full adder designs offer robust performance but suffer from excessive power consumption and large layout area at advanced nodes. This thesis presents the design, implementation, and comparative analysis of three compact 10-transistor (10T) full adder architectures—CMOS-based, SERF-based (Static Energy Recovery Full Adder), and GDI-based (Gate Diffusion Input)—across 180nm, 90nm, and 45nm CMOS technology nodes using Cadence Virtuoso. These designs were evaluated for average power consumption, propagation delay, power-delay product (PDP), and layout area. Simulation results show that the 10T SERF adder achieves the lowest PDP (110.20 fJ) and fastest delay (54.8ps at 45nm), while the 10T GDI design consumes the least power (1.89μW at 45nm) and offers the smallest area. In comparison to conventional 14T and 28T architectures, the proposed 10T designs consistently demonstrate superior energy efficiency, reduced area, and improved scalability, making them suitable for next- generation low-power and high-speed digital systems. 2025-06-01T00:00:00Z http://dspace.dtu.ac.in:8080/jspui/handle/repository/22641 Title: DESIGN OF GATE DIFFUSION INPUT BASED ENERGY EFFICIENT CNTFET CIRCUITS Authors: PARMAR, YASHODA Abstract: An extensive examination of low-power digital circuit design utilizing Gate Diffusion Input (GDI) and its dynamic extensions—DGDI, DTGDI, and DMGDI cells—is presented in this major project-II report. A transient simulation of the XOR logic gate, full adders, ripple carry adder (RCA), and 2×2 multiplier is conducted using the Gate Diffusion Input (GDI) technique and its variations, namely DGDI, DTGDI, and DMGDI. The DGDI which is a merger of basic GDI cell and novel dynamic logic block. It was investigated because of the drawbacks of GDI, such as insufficient output swing and excessive delay in intricate circuits. DGDI improves performance by enhancing swing characteristics. When GDI- and DGDI- based full adders are compared, it is shown that the former significantly reduces latency while the latter increases power consumption because of its greater transistor count. However, the lower output swing at the input of dynamic block leads to lower driving capability of the transistor and hence results in higher delay. To resolve the issue in DGDI cell, the DTGDI cell is suggested. This cell Improved latency and power efficiency, which make them competitive substitutes for intricate arithmetic processes like ripple carry multipliers and adders. Comprehensive simulations using Cadence Virtuoso based on a 32nm node evaluated the performance parameters of DGDI and DTGDI cells utilizing quantitative measurements of delay, power consumption, and power-delay product (PDP) for different circuit topologies. The DTGDI-based XOR gate was shown to be 23.6% quicker than DGDI. DGDI and DTGDI have typical power consumptions of 1.62 μW and 1.54 μW, respectively. The findings confirm the advantages of integrating dynamic logic into GDI-based designs, paving the way for more efficient, low-power digital systems. Furthermore, three transistors are used to implement XOR logic in a static logic-based MGDI cell. Compared to a GDI cell, it employs one fewer transistor since the MGDI cell implementation does not use the inverting input. As a result, the dynamic cell that is produced using MGDI, known as DMGDI, also has improved performance metrics. 2025-05-01T00:00:00Z http://dspace.dtu.ac.in:8080/jspui/handle/repository/22553 Title: DESIGN AND PERFORMANCE ANALYSIS OF AN IMPROVED LOW-POWER 8T SRAM CELL FOR ENHANCED WRITABILITY Authors: VISHWAKARMA, AKHILESH Abstract: In modern electronics, memory is a core component that enables data storage and retrieval, but cache memory is even more critical due to its direct connection to the CPU. Cache memory is designed to provide the processor with quick access to frequently used data and instructions. It relies on millions of SRAM cells, which must be highly efficient to maintain performance. These cells are required to operate with low power both static and dynamic while ensuring data remains stable and accessible. Fast read response times are also essential so that the processor is not bottlenecked during execution. This review discusses the core elements of SRAM cell design and how they impact performance. It starts by explaining why SRAM matters in computing systems and how each cell functions. The focus is placed on data stability, speed during read and write operations, and minimizing power consumption. The review explores different cell architectures and the trade-offs they involve. It addresses key design challenges, including sensitivity to noise and issues caused by manufacturing variations. It also covers improvements such as assist techniques and feedback loops. The impact of shrinking technology nodes on these cells is reviewed in detail. The performance of SRAM cells is evaluated by analyzing factors like read and write delay, write margin, stability, and power usage. This review explores how variations in design elements such as transistor sizes, supply voltage, and output loading affect these characteristics. It also looks into how process fluctuations impact the reliability and yield of SRAM cells and outlines possible solutions to enhance long-term performance and stability. This work presents a detailed Monte Carlo analysis of various 7T and 8T SRAM cell topologies at the 45nm technology node, simulated using the Cadence Virtuoso tool. The primary focus is to evaluate and compare the static and dynamic characteristics of these designs against a newly proposed 8-transistor SRAM cell, named 8TSEDPP. The analysis encompasses critical design metrics such as Hold Static Noise Margin (HSNM), Read Static vi Noise Margin (RSNM), Write Margin (WM or N-Curve), dynamic power consumption, and access times for read and write operations. The proposed 8TSEDPP circuit stands out with significant improvements in stability, power efficiency, and performance balance. In terms of RSNM, the proposed cell achieves 205 mV, outperforming all other designs, including 7TDESPP and 7TSESPK, with an average improvement of over 45%. The Write Margin also shows a notable enhancement, reaching 510.41 mV, which represents a 13.5% increase over traditional 7T cells like 7TDESPC and 7TDESPL. Despite being a more complex circuit, the dynamic power consumption of the proposed 8TSEDPP is just 317.8 nW, which is a remarkable 67.6% reduction compared to the baseline 7TDESPT design. This makes the proposed cell highly suitable for low-power applications without sacrificing stability. Timing analysis further strengthens the case for 8TSEDPP. The Write ‘0’ access time is measured at 205 ps, while Write ‘1’ access time is 291.6 ps, both of which remain within acceptable limits for high-performance applications. Although some 7T cells exhibit slightly faster access times, they lag significantly in power and noise margin performance. The Read Access Time of 510.41 ps, although not the fastest, offers a balanced trade-off given the robustness in other areas. Overall, the 8TSEDPP SRAM cell demonstrates the best overall balance across all performance, stability, and power metrics, validating its suitability for energy-sensitive and high- reliability memory applications. The proposed design is particularly promising for next-generation VLSI circuits used in portable, embedded, and IoT-based devices, where low leakage, reliable write operations, and immunity to process variations are critical. The results obtained through extensive simulations confirm that 8TSEDPP is a strong candidate for replacing or complementing traditional SRAM architectures in future semiconductor designs. 2025-05-01T00:00:00Z