http://dspace.dtu.ac.in:8080/jspui/handle/123456789/81 2026-07-01T08:28:38Z http://dspace.dtu.ac.in:8080/jspui/handle/repository/22929 Title: A LOW POWER HIGH VOLTAGE HIGH FREQUENCY PULSER CIRCUIT DESIGN FOR DENTAL APPLICATION Authors: PM, THIVYA SEKHAR; KAPOOR, RAJIV (SUPERVISOR) Abstract: The design of compact high voltage pulser circuits capable of operating at high fre quencies of MHz range remains as a big challenge in modern electronic and biomedi cal engineering fields. Existing pulser circuit design operate at single digit MHz pulse frequency ranges with low repetition rates. Conventional switching and transformer based designs suffer from various switching losses, distorted waveforms and reduced efficiency at high frequencies. This thesis is focused to address this gap of research by presenting the design and simulation results of a voltage pulser circuit design that is ca pable of generating 300V pulses with pulse frequencies ranging from 39kHz to 20MHz with a variable repetition frequency. The design includes a frequency divider circuit, a pulse transformer for transmitting the voltage pulse and analog-digital converters and a microcontroller for further processing the received signal. The proposed design makes use of flip flop based frequency divider circuit to get pulses at various frequencies and a frequency selector topology implemented using ANDlogic. Apulse transformer topology is used to amplify the selected pulse voltage upto 300V. Simulation results show a voltage pulses that has peak voltage above 300V for the required pulse width duration and voltage droop of 20V to 40V. It is also ob served that all the pulse have a 50% duty cycle with rise times of less than 8% of pulse width and fall times of less than 8% of pulse width. Simulation results show an out put current in milliamperes with a power from a 5V DC source. The proposed design serves as a foundation for further study of high voltage high frequency voltage pulser circuit that have uses in dental devices as well as in applications that necessitate such a pulser circuit. 2026-06-01T00:00:00Z http://dspace.dtu.ac.in:8080/jspui/handle/repository/22920 Title: AYOLO-BASEDSYSTEMFORREAL-TIME DETECTIONOFDEFECTS INPRINTED CIRCUIT BOARDS Authors: VARMA, GADIRAJU NARENDRA; VERMA, O.P. (SUPERVISOR) Abstract: Printed Circuit Boards (PCBs) are the backbone of modern electronic devices and quality of PCB is paramount for reliability of the system. Traditional inspection tech niques for PCB defects by human hand are generally slow, laborious and not very pre cise in the case of defects which are very small and intricate.This paper provides a framework for automated inspection system for PCBs based on a YOLO (You Only Look Once) architecture which is coupled with a Single Head Self-Attention (SHSA) mechanism to boost the feature representation and inspection ability. The aim is to detect various type of PCB defects using the combination of real-time detection by YOLO and attention based reasoning provided by SHSA to enhance the importance of feature regions and minimize redundancy from backgrounds. Attention mechanism learns the feature space of defect categories by paying special attention to the signif icant features while disregarding backgrounds in image thereby making the detection of defects, with different sizes, shapes, and intensity variations, robust. The system analyzes PCB image, extracts distinctive features and predicts bounding box for defect regions. This framework is composed of stages such as data preprocessing, feature extraction, multi scale feature fusion, attention enhancement, and detection of defects. These defect classes in PCBs are annotated to train and test the deep learning based object detection system. The experimental validation has been done by reporting vari ous object detection metrics like Precision, Recall, mean Average Precision (mAP) and inference speed. From the empirical results, it is evident that attention mechanisms are beneficial for capturing intricate features and enhancing defect detection accuracy in PCBs. The present work highlights the significance of attention based feature enrich ment along with real time object detection technique for industrial automation. The proposed system is extensible and feasible for automating the industrial inspection. 2026-06-01T00:00:00Z http://dspace.dtu.ac.in:8080/jspui/handle/repository/22917 Title: DEEP LEARNING BASED PROPAGATION DELAY PREDICTION AND SENSITIVITY ANALYSIS OF CMOS LOGIC CIRCUITS Authors: NEGI, ANKITA; Suneja, Kriti (SUPERVISOR) Abstract: Propagation delay is one of the most critical performance parameters in CMOS digital circuit design, directly influencing timing closure, clock frequency, and overall system performance. As VLSI technology scales to nanometer nodes, accurate and efficient estimation of propagation delay becomes increasingly important during the design phase. Traditional SPICE-based simulation methods, while highly accurate, are computationally intensive and become impractical for large scale design optimization and exploration. This thesis proposes a deep learning-based approach for predicting propagation delay in fundamental CMOS logic gates — inverter, 2-input NAND, and 2 input NOR — at the 45 nm technology node. A comprehensive dataset of 2500 simulation samples is generated using SPICE-based circuit simulation by varying key circuit parameters including NMOS transistor width (Wn), PMOS transistor width (Wp), channel length (L), supply voltage (VDD: 0.8–1.2 V), load capacitance (CL: 1–20 fF), and temperature (0–100°C). Feature engineering techniques are employed to derive additional physically meaningful parameters such as the transistor width ratio (Wp/Wn) and the RC time constant product. A multilayer perceptron (MLP) based deep learning regression model is developed and trained on the preprocessed dataset. 2026-05-01T00:00:00Z http://dspace.dtu.ac.in:8080/jspui/handle/repository/22916 Title: FGMOS BASED VDTA REALIZATIONS WITH ENHANCED PERFORMANCE Authors: SAXENA, ARUSHI; Pandey, Rajeshwari (SUPERVISOR) Abstract: This thesis presents a comparative study of floating-gate MOSFET-based voltage differencing transconductance amplifier realizations with the objective of improving low-voltage operation and transconductance performance for analog signal-processing applications. This work consolidates two research studies carried out during the M. Tech. program, both using the CMOS VDTA as the reference architecture and then explore circuit modifications at the input transconductance stage. In the first study, FGMOS devices are introduced to exploit the capacitive gate coupling and threshold voltage modulation. Then, partial positive feedback is subsequently employed to enhance the effective transconductance. In the second study, a series parallel current mirror is incorporated to further boost transconductance while preserving the low-voltage benefits of the FGMOS-based structure. All circuits are simulated in 180 nm CMOS technology using LTspice under identical supply and biasing conditions to ensure a fair comparison. The simulation results show that the conventional CMOS VDTA provides a transconductance of 1.27 mS with a bandwidth of 405.7 MHz, whereas the FGMOS-based realization supports low-voltage operation and exhibits modified frequency behaviour with a bandwidth improvement. The PPF-enhanced design increases transconductance to 1.84 mS with a bandwidth reduction to 148 MHz, while the SPCM-enhanced implementation achieves the highest transconductance of 4.23 mS, with bandwidth of 126.3 MHz. Overall, the findings demonstrate that FGMOS-based VDTA architectures are effective for low-voltage analog design, while PPF and SPCM techniques offer significant transconductance boost with the expected gain-bandwidth trade-off. 2026-06-01T00:00:00Z