http://dspace.dtu.ac.in:8080/jspui/handle/123456789/81 2026-04-28T04:03:51Z 2026-04-28T04:03:51Z BHATT, KAVITA http://dspace.dtu.ac.in:8080/jspui/handle/repository/22672 2026-02-24T09:03:48Z 2026-02-01T00:00:00Z

Title: DESIGN OF EFFICIENT ALGORITHMS FOR BRAIN DISEASE IDENTIFICATION AND CLASSIFICATION Authors: BHATT, KAVITA Abstract: Brain diseases encompass a wide range of disorders, such as neurodegenerative disorders, cerebrovascular disorders, neurodevelopmental disorders, seizure disorders, and brain tumors that impair cognitive, motor, and behavioral functions of human beings. Among these disorders, neurodegenerative disorders are considered the most prominent brain disorders due to their progressive nature, which leads to a continuous decline in cognitive, motor, and behavioral functions. Unlike other brain disorders, these disorders worsen over time and currently have no definitive cure, which makes them a major challenge for healthcare systems worldwide. Alzheimer’s Disease (AD) and Parkinson’s Disease (PD) are the two most prevalent neurodegenerative disorders, affecting millions of people worldwide and imposing substantial social and economic burdens. AD primarily causes progressive memory loss and cognitive decline due to amyloid plaques and tau tangles, while PD mainly leads to motor and non-motor symptoms like tremor, rigidity, and bradykinesia due to dopaminergic neuron loss and Lewy bodies. Both AD and PD are irreversible, progressive neurodegenerative disorders with no particular cure, leading to a gradual decline in cognitive and motor functions and a significant deterioration in patients’ quality of life. Although the progression of these disorders can be slowed with certain medications and therapies. Early and accurate diagnosis is essential to provide timely and effective interventions. Therefore, early detection is crucial for ensuring the much-needed care and support for patients. This thesis aims to develop optimized, automated frameworks for early and ac- curate identification of these brain diseases using biomedical signal analysis and advanced machine learning (ML) and deep learning (DL) techniques. Biosignaling modalities such as electroencephalography (EEG), gait analysis, and speech pattern assessment are cost-efficient and non-invasive in nature. These signals capture essen- tial physiological and behavioral markers reflecting neurological impairments. These iv modalities enable the detection of subtle abnormalities in brain activity, motor func- tion, and communication, providing valuable insights into the onset and progression of neurodegenerative disorders without the need for invasive or expensive clinical procedures. Biomedical signals are typically high-dimensional and contain redundant or ir- relevant information. Identifying the most informative and discriminative features is crucial to improving classification accuracy and computational efficiency. Hence, feature selection-driven optimization models are developed for brain disease detection. For PD, EEG datasets obtained from OpenNeuro are analyzed using statistical and ensemble-based feature selection methods. The Kruskal–Wallis test and Extra tree classifier (ETC) are used to select the most discriminative EEG features. Additionally, a two-stage PD detection framework is developed to enhance diagnostic accuracy and computational efficiency. Initially, an ETC-based feature selection is employed to obtain the most relevant and discriminative speech features while eliminating re- dundant or non-informative ones. These optimal feature subsets effectively reduced dimensionality and improved the model’s ability to capture meaningful variations associated with PD. To address the issue of class imbalance commonly observed in biomedical datasets, the synthetic minority oversampling technique is applied to generate synthetic samples for the minority class. This ensured balanced training data and prevented bias toward the majority class. Then, a stacked ensemble model is em- ployed for classification, which leverages the complementary strengths of individual classifiers. The proposed two-stage framework significantly improved classification performance for PD detection using speech signals. Identifying the most affected brain regions and corresponding EEG channels is crucial for achieving accurate diagnosis and meaningful neuroscientific interpretation in AD. AD causes progressive neurodegeneration that disrupts neuronal connectivity and alters the brain’s rhythmic activity patterns. These abnormalities are not uniformly distributed but are concentrated in specific cortical areas. Therefore, it is essential to analyze EEG signals across multiple lobes: frontal, temporal, parietal, and occipital lobes to identify the dominant brain regions and EEG channels most influenced by v the disease. Identifying these regions enhances the interpretability of ML models, strengthens the physiological validity of classification outcomes, and supports targeted clinical assessments for early and precise AD diagnosis. For this purposes, a Fourier decomposition and Hilbert transform-based EEG signal analysis (FHESA) method is developed. The FHESA method integrates the Fourier Decomposition Method (FDM) and Hilbert Transform (HT) to extract meaningful features from the EEG signal for efficient classification and brain region analysis. The FHESA method aims to efficiently analyze the EEG data to identify the important brain regions vulnerable to AD, and to assess the impact of various EEG channels for the timely and early detection of AD. The accurate detection and classification of neurological disorders is one of the most challenging tasks due to the overlapping clinical symptoms and shared patholog- ical characteristics of diseases such as AD and Frontotemporal dementia (FTD). Both disorders lead to progressive cognitive decline and behavioral impairments, often resulting in misdiagnosis and delayed treatment. Traditional diagnostic methods heav- ily rely on neuroimaging and clinical assessments, which are both time-consuming and costly. Moreover, biomedical signals such as EEG exhibit non-linear and non- stationary behavior, making it difficult for conventional machine learning methods to capture underlying temporal–spectral dependencies. Therefore, there is a need for an algorithm that can extract robust, noise-invariant, and discriminative features capable of representing complex brain activities associated with different neurological conditions. To address this, wavelet scattering transform-based dementia identification and classification (WavDemNet) is proposed. The model leverages the wavelet scatter- ing transform (WST) to extract robust, noise-invariant features that capture essential time-frequency characteristics and a 1-D convolutional neural network (CNN) to learn discriminative patterns for accurate identification and classification of brain diseases. Manual analysis of biomedical signals is time-consuming. To assist clinicians in real-time decision-making, there is a requirement to develop automated and ef- ficient algorithms that can process signals, extract optimal features, and accurately classify neurological disorders with minimal human intervention. For this purpose, an vi automated algorithmic framework is developed for the early diagnosis of PD. The high- resolution superlet transform (SLT) technique is utilized to obtain the time-frequency representation (TFRs) of the signal. SLT employs multiple wavelets to achieve higher TF resolution while being less leaky than a single wavelet, which makes it more sus- tainable to apply to non-stationary signals. In order to identify PD and assess the PD severity rate, the TFRs are fed into deep neural network (DNN) models as input. This approach eliminates the need of additional handcrafted feature extraction methods, as the DNNs are capable of automatically learning hierarchical and discriminative patterns from the TFRs. This model captures signal variations associated with PD progression and results in accurate detection and severity assessment.

2026-02-01T00:00:00Z PUSHKAR, TVISHA http://dspace.dtu.ac.in:8080/jspui/handle/repository/22643 2026-02-10T04:46:39Z 2025-06-01T00:00:00Z

Title: SIGNAL GENERATION AND PROCESSING APPLICATIONS USING CURRENT MODE BUILDING BLOCKS Authors: PUSHKAR, TVISHA Abstract: This thesis presents a comprehensive study on signal generation and processing using current-mode active building blocks (ABBs), specifically focusing on the Universal Voltage Conveyor (UVC) and the Voltage Differencing Buffered Amplifier (VDBA). These elements represent a significant advancement in analog signal processing, offering improved performance in speed, linearity, power efficiency, and CMOS compatibility over traditional voltage-mode circuits. The work addresses key bottlenecks in existing oscillator and filter designs by developing novel circuit architectures that are compact, low-power, and capable of robust and tunable operation under practical non-idealities. The research is structured in four parts. The first part introduces the foundational principles of analog signal processing and the advantages of current-mode operation. It also presents a literature review on the evolution and applications of UVC and VDBA, identifying gaps in tuning flexibility, harmonic distortion, and sensitivity to component variations. Particular attention is given to the third-order quadrature sinusoidal oscillator (TOQSO) and multiple-input single-output (MISO) universal filter designs. The second part of the thesis proposes two innovative circuits: an improved TOQSO using UVC and a compact, electronically tunable MISO universal filter using VDBA. The proposed TOQSO achieves independent control over the frequency of oscillation (FO) and condition of oscillation (CO), reducing total harmonic distortion (THD) to below 1.5%, a marked improvement over existing OTA- and CCII-based designs. The MISO filter, designed using a single VDBA, two grounded capacitors, and one resistor, realizes all five second-order filter responses (low-pass, high-pass, band-pass, band-reject, and all- vii pass) without the need for reconfiguration. Both circuits exploit the strengths of their respective ABBs to address the shortcomings of earlier designs. In the third part, rigorous mathematical modeling is presented for both circuits, followed by detailed sensitivity analysis that confirms the low dependence of key parameters (ω₀ and Q) on passive component variations. SPICE simulations using 0.18 μm CMOS technology validate the theoretical predictions. For the TOQSO, output waveforms, frequency spectra, and Lissajous patterns confirm sinusoidal oscillation with quadrature phase accuracy and spectral purity. For the MISO filter, frequency response plots for each mode demonstrate accurate cutoff and center frequencies. Simulation results align closely with analytical derivations. To bridge the gap between simulation and real-world applicability, experimental prototypes of both designs were implemented using commercially available ICs. The TOQSO exhibited stable sinusoidal outputs with precise 90° phase difference, and the filter achieved consistent performance across a frequency range from 10.5 kHz to 500.5 kHz. These results confirm the feasibility and robustness of the proposed circuits under practical conditions, including non-idealities such as voltage tracking errors and finite transconductance mismatches. A comparative performance analysis against conventional designs—OTA-, CCII-, and CDBA-based—demonstrates the superiority of the proposed solutions in terms of spectral purity, power efficiency, component count, and CMOS integration readiness. The VDBA- based filter exhibits lower power consumption and higher Q-factor than its counterparts, while the UVC-based oscillator outperforms in frequency stability and THD. The thesis concludes by outlining the broader implications of these findings. The proposed designs contribute to the advancement of low-voltage, low-power analog front-end systems, particularly in wearable biomedical devices, adaptive communication systems, sensor interfaces, and energy-constrained IoT nodes. Their compactness and simplicity make them ideal candidates for integration into modern VLSI systems. viii Future directions for research include extending these architectures for fully electronically tunable operation, deploying them in multi-band or reconfigurable systems, and implementing them in deep-submicron or emerging device technologies such as FinFETs and CNTFETs. Furthermore, integrating these circuits into system-on-chip (SoC) solutions for biomedical and communication applications could significantly enhance performance and miniaturization. Through its dual focus on theoretical rigor and practical validation, this thesis contributes to the evolving landscape of analog signal processing, establishing reliable and efficient building blocks for next-generation analog integrated circuits.

2025-06-01T00:00:00Z TALHA, MOHAMMAD http://dspace.dtu.ac.in:8080/jspui/handle/repository/22642 2026-02-10T04:46:30Z 2025-06-01T00:00:00Z

Title: DESIGN AND COMPARATIVE ANALYSIS OF A DIFFERENT FULL ADDERS FOR LOW POWER AND HIGH-SPEED VLSI APPLICATIONS ACROSS TECHNOLOGY NODES Authors: TALHA, MOHAMMAD Abstract: With the continued scaling of CMOS technology into deep submicron regions, achiev- ing a balance between low power consumption and high-speed operation has become essential in digital arithmetic units. The full adder, a fundamental building block in arithmetic logic units (ALUs), has been widely studied to reduce power, delay, and area metrics. Traditional 28-transistor (28T) and 14-transistor (14T) full adder designs offer robust performance but suffer from excessive power consumption and large layout area at advanced nodes. This thesis presents the design, implementation, and comparative analysis of three compact 10-transistor (10T) full adder architectures—CMOS-based, SERF-based (Static Energy Recovery Full Adder), and GDI-based (Gate Diffusion Input)—across 180nm, 90nm, and 45nm CMOS technology nodes using Cadence Virtuoso. These designs were evaluated for average power consumption, propagation delay, power-delay product (PDP), and layout area. Simulation results show that the 10T SERF adder achieves the lowest PDP (110.20 fJ) and fastest delay (54.8ps at 45nm), while the 10T GDI design consumes the least power (1.89μW at 45nm) and offers the smallest area. In comparison to conventional 14T and 28T architectures, the proposed 10T designs consistently demonstrate superior energy efficiency, reduced area, and improved scalability, making them suitable for next- generation low-power and high-speed digital systems.

2025-06-01T00:00:00Z PARMAR, YASHODA http://dspace.dtu.ac.in:8080/jspui/handle/repository/22641 2026-02-10T04:46:21Z 2025-05-01T00:00:00Z

Title: DESIGN OF GATE DIFFUSION INPUT BASED ENERGY EFFICIENT CNTFET CIRCUITS Authors: PARMAR, YASHODA Abstract: An extensive examination of low-power digital circuit design utilizing Gate Diffusion Input (GDI) and its dynamic extensions—DGDI, DTGDI, and DMGDI cells—is presented in this major project-II report. A transient simulation of the XOR logic gate, full adders, ripple carry adder (RCA), and 2×2 multiplier is conducted using the Gate Diffusion Input (GDI) technique and its variations, namely DGDI, DTGDI, and DMGDI. The DGDI which is a merger of basic GDI cell and novel dynamic logic block. It was investigated because of the drawbacks of GDI, such as insufficient output swing and excessive delay in intricate circuits. DGDI improves performance by enhancing swing characteristics. When GDI- and DGDI- based full adders are compared, it is shown that the former significantly reduces latency while the latter increases power consumption because of its greater transistor count. However, the lower output swing at the input of dynamic block leads to lower driving capability of the transistor and hence results in higher delay. To resolve the issue in DGDI cell, the DTGDI cell is suggested. This cell Improved latency and power efficiency, which make them competitive substitutes for intricate arithmetic processes like ripple carry multipliers and adders. Comprehensive simulations using Cadence Virtuoso based on a 32nm node evaluated the performance parameters of DGDI and DTGDI cells utilizing quantitative measurements of delay, power consumption, and power-delay product (PDP) for different circuit topologies. The DTGDI-based XOR gate was shown to be 23.6% quicker than DGDI. DGDI and DTGDI have typical power consumptions of 1.62 μW and 1.54 μW, respectively. The findings confirm the advantages of integrating dynamic logic into GDI-based designs, paving the way for more efficient, low-power digital systems. Furthermore, three transistors are used to implement XOR logic in a static logic-based MGDI cell. Compared to a GDI cell, it employs one fewer transistor since the MGDI cell implementation does not use the inverting input. As a result, the dynamic cell that is produced using MGDI, known as DMGDI, also has improved performance metrics.

2025-05-01T00:00:00Z