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Browsing by Subject CMOS TECHNOLOGY
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Showing results 1 to 20 of 30
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Issue Date
Title
Author(s)
2024-05
A 12-Bit 1.2-GS/s CURRENT-STEERING DAC in 45-nm CMOS TECHNOLOGY
GUPTA, TARUN
2018-07
6T SRAM HIGH DENSITY BIT-CELL ANALYSIS FOR 1PPM FAILURE RATE TARGETTING TEMPERATURE (-40,165)
SINGH, ANUKRITI
2011-07
ANALOG FILTER DESIGN USING OTA
KUMAR, SUNIL
2024-12
ANALYSIS AND DESIGN OF CMOS MULTISTAGE AMPLIFIERS
GUPTA, OM KRISHNA
2026-06
ANALYSIS OF LOW-POWER 2:1 MULTIPLEXERUSING DMLANDLDMLTECHNIQUES
ANAND, NIKITA
;
NAND, DEVA (SUPERVISOR)
2016-07
APPLICATIONS OF ELECTRONICALLY TUNABLE OTA
TANWER, KAMLESH KUMAR
2022-05
BLOCK LEVEL TIMING AND POWER OPTIMIZATION OF VLSI PHYSICAL DESIGN
GUPTA, SANDEEP KUMAR
2026-05
DESIGN AND ANALYSIS OF HIGH-SPEED CMOS VOLTAGE LEVEL SHIFTERS FOR SUB-THRESHOLD VOLTAGE REGIME
DIMRI, AYUSH
;
KUMAR, CHAUDHRY INDRA (SUPERVISOR)
2017-07
DESIGN AND ANALYSIS OF LNA FOR 2.4 GHZ ISM BAND USING 0.13 µm CMOS TECHNOLOGY
ADITI
2025-05
DESIGN AND ANALYSIS OF LOW POWER COMBINATIONAL CIRCUIT USING REVERSIBLE GATE
HAFEEZ, ASMAR
2025-06
DESIGN AND COMPARATIVE ANALYSIS OF A DIFFERENT FULL ADDERS FOR LOW POWER AND HIGH-SPEED VLSI APPLICATIONS ACROSS TECHNOLOGY NODES
TALHA, MOHAMMAD
2021-06
DESIGN OF A NOVEL TERNARY D FLIP-FLOP BASED ON GNRFET
PATHAK, SHASHANK
2024-05
DESIGN OF LOW LEAKAGE SRAM CELLS WITH ENHANCED STABILITY FOR NEAR THRESHOLD VOLTAGE REGIME
BHATIA, RACHIT
2023-05
ENERGY EFFICIENT VOLTAGE LEVEL SHIFTER DESIGN IN NTV REGIME
RIKHARI, MOHIT
2025-11
HIGH PERFORMANCE SRAM DESIGN
SONI, LOKESH
2017-07
IMPLEMENTATION OF ANALOG CIRCUITS USING CDTA AND CDDITA
SURESHRAO, AMBATKAR HARSHAL
2016-10
IMPLEMENTATION OF VARIOUS FILTERS USING OTRA
HARSH, AMAN
2013-07-11
Layout Area Optimization of 1-Bit CMOS Full Adder Using Genetic Algorithm
Mayank kumar
2025-12
REALISATION OF SIMULATED IMMITTANCES USING MODERN ACTIVE BUILDING BLOCKS
SHRIVASTAVA, MEGHANA
2016-10
REALIZATION OF DELAY LOCKED LOOP USING VCDL IN 180NM CMOS TECHNOLOGY
DAHARIA, HIMANSHU
